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1. general description the lpc540xx is a family of arm cortex-m4 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption and enhanced debug features. the arm cortex-m4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a hi gh level of support block integration. the arm cortex-m4 cpu incorporates a 3-stage pi peline, uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital si gnal processing and simd instructions. a hardware floating-point processor is integrated into the core. the lpc540xx family includes 360 kb of on-chip sram, a quad spi flash interface (spifi) for expanding program memory, one high-speed and one full-speed usb host and device controller, ethernet avb, lcd contro ller, smart card inte rfaces, sd/mmc, can fd, an external memory controller (emc), a dmic subsystem with pdm microphone interface and i 2 s, five general-purpose timers, sctimer/pwm, rtc/alarm timer, multi-rate timer (mrt), a windowed watc hdog timer (wwdt), ten flexible serial communication peripherals (usart, spi, i 2 s, i 2 c interface), secure hash algorithm (sha), 12-bit 5.0 msamples/sec adc, and a temperature sensor. 2. features and benefits ? arm cortex-m4 core (version r0p1): ? arm cortex-m4 processor, running at a frequency of up to 180 mhz. ? floating point unit (fpu) and memory protection unit (mpu). ? arm cortex-m4 built-in nested vect ored interrupt controller (nvic). ? non-maskable interrupt (nmi) in put with a selection of sources. ? serial wire debug (swd) with six instruct ion breakpoints, two literal comparators, and four watch points. includes serial wire output and etm trace for enhanced debug capabilities, and a debug timestamp counter. ? system tick timer. ? on-chip memory: ? up to 360 kb total sram consisting of 160 kb contiguous main sram and an additional 192 kb sram on the i&d buses. 8 kb of sram bank intended for usb traffic. lpc540xx 32-bit arm cortex-m4 microc ontroller; 360 kb sram; high-speed usb device/hos t + phy; full-speed usb device/host; ethernet avb; lcd; emc; spifi; can fd, sdio; 12-bit 5 msamples/s ad c; dmic subsystem rev. 1.8 ? 22 june 2018 product data sheet
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 2 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? general-purpose one-time programmable (otp) memory for user application specific data ? rom api support: ? in-application programming (iap) and in-system programming (isp). ? rom-based usb drivers (hid, cdc, msc, and dfu). ? supports serial interface booting (uart, i2c, spi) from an application processor, automated booting from nor flash (quad spi fi, 8/16/32-bit external parallel flash), and usb booting (full-speed, high-speed). ? fro api for selecting fro output frequency. ? otp api for programming otp memory. ? random number generator (rng) api. ? execute in place (xip) from spifi nor flash (in quad, dual spifi mode or single-bit spi mode), and parallel nor flash. ? serial interfaces: ? flexcomm interface contains up to 11 serial peripherals. each flexcomm interface (except flexcomm 10, which is dedicated for spi) can be selected by software to be a usart, spi, or i2c interface. two flexcomm interfaces also include an i2s interface. each flexcomm interface incl udes a fifo that supports usart, spi, and i2s if supported by that flexcomm inte rface. a variety of clocking options are available to each flexcomm interface an d include a shared fractional baud-rate generator. ? i2c-bus interfaces support fast-mode and fast-mode plus with data rates of up to 1mbit/s and with multiple address recognition and monitor mode. two sets of true i2c pads also support high speed mode (3.4 mbit/s) as a slave. ? two iso 7816 smart card interfaces with dma support. ? usb 2.0 high-speed host/device controller with on-chip high-speed phy. ? usb 2.0 full-speed host/device controlle r with on-chip phy and dedicated dma controller supporting crystal-less operation in device mode using software library. see technical note tn00033 for more details. ? spifi with xip feature uses up to four data lines to access off-chip spi/dspi/qspi flash memory at a much higher rate than standard spi or ssp interfaces. ? ethernet mac with mii/rmii in terface with audio video bridging (avb) support and dedicated dma controller. ? two can fd modules with dedicated dma controller. ? digital peripherals: ? dma controller with 32 channels and up to 24 programmable triggers, able to access all memories and dma-capable peripherals. ? lcd controller supporting both super- twisted nematic (stn) and thin-film transistor (tft) displays. it has a dedi cated dma controller, selectable display resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode. ? external memory controller (emc) provid es support for asynchronous static memory devices such as ram, rom and fl ash, in addition to dynamic memories such as single data rate sdram with an sdram clock of up to 100 mhz. emc bus width (bit) on tfbga180, tfbga100, and lqfp100 packages supports up to 8/16 data line wide static memory. ? secured digital input/output (sd/mmc and sdio) card interf ace with dma support. ? crc engine block can calculate a crc on supplied data using one of three standard polynomials with dma support.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 3 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? up to 171 general-purpose input/output (gpio) pins. ? gpio registers are located on the ahb for fast access. the dma supports gpio ports. ? up to eight gpios can be selected as pin interrupts (pint), triggered by rising, falling or both input edges. ? two gpio grouped interrupts (gint) enable an interrupt based on a logical (and/or) combination of input states. ? analog peripherals: ? 12-bit adc with 12 input channels and with multiple internal and external trigger inputs and sample rates of up to 5.0 msamples/sec. the adc supports two independent conversion sequences. ? integrated temperature sensor connected to the adc. ? dmic subsystem includes a dual-channel pd m microphone interface with decimators, filtering, and hardware voice activity de tection. the processed output data can be routed directly to an i 2 s interface if needed. ? timers: ? five 32-bit general purpose timers/counters. all five timers support up to four capture inputs and four compare outputs, pwm mode, and external count input. specific timer events can be selected to generate dma requests. ? one sctimer/pwm with eight input and ten ou tput functions (inc luding capture and match). inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. internally, the sctimer/pwm supports 16 match/captures, 16 events, and 16 states. ? 32-bit real-time clock (rtc) with 1 s reso lution running in the always-on power domain. a timer in the rtc can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. ? multiple-channel multi-rate 24-bit timer (mrt) for repetitive interrupt generation at up to four programmable, fixed rates. ? windowed watchdog timer (wwdt). ? repetitive interrupt timer (rit) for debug time stamping and for general purpose use. ? security features: ? secure hash algorithm (sha1/sha2) module supports boot with dedicated dma controller. ? clock generation: ? 12 mhz internal free runni ng oscillator (fro). this oscillator provides a selectable 48 mhz or 96 mhz output, and a 12 mhz output (divided down from the selected higher frequency) that can be used as a system clock. the fro is trimmed to ? 1 % accuracy over the entire voltage and temperature range. ? crystal oscillator with an operat ing range of 1 mhz to 25 mhz. ? watchdog oscillator (wdtosc) with a fr equency range of 6 khz to 1.5 mhz. ? 32.768 khz low-power rtc oscillator. ? system pll allows cpu operation up to the maximum cpu rate and can run from the main oscillator, the internal fro, the watchdog oscillator or the 32.768 khz rtc oscillator. ? two additional plls for usb clock and audio subsystem. ? independent clocks for the spifi interfac e, adc, usbs, and the audio subsystem.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 4 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? clock output function with divider. ? frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal. ? power control: ? programmable pmu (power management un it) to minimize power consumption and to match requirements at different performance levels. ? reduced power modes: sleep, deep-sleep, and deep power-down. ? wake-up from deep-sleep modes due to activity on the usart, spi, and i2c peripherals when operating as slaves. ? ultra-low power micro-tick ti mer, running from the watc hdog oscillator that can be used to wake up the device from low power modes. ? power-on reset (por). ? brown-out detect (bod) with separate th resholds for interrup t and forced reset. ? single power supply 1.71 v to 3.6 v. ? power-on reset (por). ? brown-out detect (bod) with separate th resholds for interrup t and forced reset. ? jtag boundary scan supported. ? 128 bit unique device serial number for identification. ? operating temperature range ? 40 c to +105 c. ? available in tfbga180, tfbga100, lqfp208, and lqfp100 packages.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 5 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 3. ordering information table 1. ordering information type number package name description version lpc54018jet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-3 LPC54018JBD208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 ? 28 ? 1.4 mm sot459-1 lpc54016jet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-3 lpc54016jbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 ? 28 ? 1.4 mm sot459-1 lpc54016jbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc54016jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc54005jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc54005jbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 6 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 3.1 ordering options table 2. ordering options type number package name sram/kb fs usb hs usb ethernet avb classic can can fd lcd emc data bus width (bit) flexcomm interface gpio sha lpc54018 devices (hs/fs usb, ethernet, can 2.0+can fd, lcd, sha) lpc54018jet180 tfbga180 360 yes yes yes yes yes yes 8/16 11 145 yes LPC54018JBD208 lqfp208 360 yes yes yes yes yes yes 8/16/32 11 171 yes lpc54016 devices (hs/fs usb, ethernet, can 2.0+can fd, sha) lpc54016jet180 tfbga180 360 yes yes yes yes yes - 8/16 11 145 yes lpc54016jbd208 lqfp208 360 yes yes yes yes yes - 8/16/32 11 171 yes lpc54016jbd100 lqfp100 360 yes yes yes yes yes - 8/16 10 64 yes lpc54016jet100 tfbga100 360 yes yes yes yes yes - 8/16 10 64 yes lpc54005 devices (hs/fs usb, sha) lpc54005jet100 tfbga100 360 yes yes - - - - 8/16 10 64 yes lpc54005jbd100 lqfp100 360 yes yes - - - - 8/16 10 64 yes
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 7 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 4. marking the lpc540xx tfbga180 and tfbga100 packages have the following top-side marking: ? first line: lpc540xxj ? second line: et180 or et100 ? third line: xxxxxxxxxxxx ? fourth line: xxxyywwx[r]x ? yyww: date code with yy = year and ww = week. ? xr = boot code version and device revision. the lpc540xx lqfp208 and lqfp100 packages have the following top-side marking: ? first line: lpc540xxj ? second line: bd208 or bd100 ? third line: xxxxxxxxxxxx ? fourth line: xxxyywwx[r]x ? yyww: date code with yy = year and ww = week. ? xr = boot code version and device revision. fig 1. tfbga180 and tfbga 100 package markings fig 2. lqfp208 package marking terminal 1 index area aaa-025721 1 n terminal 1 index area aaa-011231 fig 3. lqfp100 package marking 1 n terminal 1 index area aaa-029374
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 8 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller table 3. device revision table revision identifier (r) revision description 0a initial device revision with boot rom version 21.0
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 9 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 5. block diagram figure 4 shows the lpc540xx block diagram. in th is figure, orange sh aded blocks support general purpose dma and yellow shaded blocks include dedicated dma control.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 10 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 4. lpc540xx block diagram debug interface isp access port jtag test and boundary scan interface ethernet phy interface lcd panel sdio interface can interface fs usb bus arm cortex-m4 with fpu/mpu d-code bus system bus i-code bus aaa-029063 general purpose dma controller ethernet 10/100 mac +avb lcd panel interface usb 2.0 host/ device hd sdio can fd can fd sha clocks and controls internal power clock generation, power control, and other system functions voltage regulator xtalin xtalout rst clk out spifi adc inputs d[31:0] a[25:0] control gpio vdd hs usb phy boot rom 64 kb sram 192 kb sram 32 kb sram 32 kb sram 32 kb 12b adc 12-ch temp sensor polyfuse otp 256 b static/dynamic ext memory controller hs usb host registers fs usb host registers sha slave interface usb ram interface sram 8 kb spi flash interface sram 64 kb hs usb bus hs gpio 0-5 fs usb device registers lcd registers dma registers emc registers spifi registers multilayer ahb matrix sctimer/ pwm flexcomms 0-4 -uarts 0-4 - i2cs 0-4 -spi0s 0-4 crc engine hs usb device registers audio subsys d-mic, decimator, etc ethernet registers can 1 registers ahb to apb bridge ahb to apb bridge async ahb to apb bridge can 0 registers system control apb slave group 0 sdio registers flexcomms 5-9 -uarts 5-9 -spi0s 5-9 -i2cs 5-9 - i2ss 0,1 i/o configuration note: - orange shaded blocks support gen. purpose dma. - yellow shaded blocks include dedicated dma ctrl. gpio global intrpts (0, 1) gpio interrupt control periph input mux selects 2 x 32-bit timers (t0, 1) pmu regs (+bb, pvt) apb slave group 1 32-bit timers (t2) system control (async regs) apb slave group 2 2 x 32-bit timers (t3, 4) rit 2 x smartcards random number gen real time clock 32 khz osc rtc alarm rtc power domain divider multi-rate timer otp controller watchdog osc windowed wdt micro tick timer
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 11 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 6. pinning information 6.1 pinning fig 5. tfbga 180 pin configuration fig 6. tfbga 100 pin configuration aaa-026026 246810121314 1357911 ball a1 index area p n m l k j g e h f d c b a transparent t op view aaa-029079 transparent top view j g k h f e d c b a 246810 13579 ball a1 index area
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 12 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 7. lqfp 208 pin configuration fig 8. lqfp 100 pin configuration 156 53 104 208 157 105 1 52 aaa-02602 7 50 1 25 75 51 26 76 100 aaa-029081
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 13 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 6.2 pin description on the lpc540xx, digital pins are grouped into several ports. each digital pin can support several different digital functions (inclu ding general purpose i/o (gpio)) and an additional analog function. table 4. pin description symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description pio0_0 c4 d6 196 93 [2] pu; z i/o pio0_0 ? general-purpose digital input/output pin. remark: in isp mode, this pin is set to the flexcomm 3 spi sck function. i can1_rd ? receiver input for can 1. i/o fc3_sck ? flexcomm 3: usart or spi clock. o ctimer_mat0 ? match output 0 from timer 0. i sct0_gpi0 ? pin input 0 to sctimer/pwm. o pdm0_clk ? clock for pdm interface 0, for digital microphone. pio0_1 a1 a1 207 100 [2] pu; zpu; z i/o pio0_1 ? general-purpose digital input/output pin. remark: in isp mode, this pin is set to the flexcomm 3 spi ssel0 function. o can1_td ? transmitter output for can 1. i/o fc3_cts_sda_ssel0 ? flexcomm 3: usart clear-to-send, i2c data i/o, spi slave select 0. i ct0_cap0 ? capture input 0 to timer 0. i sct0_gpi1 ? pin input 1 to sctimer/pwm. i pdm0_data ? data for pdm interface 0 (digital microphone). pio0_2/ trst a7 e9 174 83 [2] pu; z i/o pio0_2 ? general-purpose digital input/output pin. in boundary scan mode: trst (test reset). remark: in isp mode, this pin is set to the flexcomm 3 spi miso function. i/o fc3_txd_scl_miso ? flexcomm 3: usart transmitter, i2c clock, spi master-in/slave-out data. i ct0_cap1 ? capture input 1 to timer 0. o sct0_out0 ? sctimer/pwm output 0. i sct0_gpi[2] ? pin input 2 to sctimer/pwm. i/o emc_d[0] ? external memory in terface data [0].
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 14 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_3/ tck a6 a10 178 85 [2] pu; z i/o pio0_3 ? general-purpose digital input/output pin. in boundary scan mode: tck (test clock in). remark: in isp mode, this pin is set to the flexcomm 3 spi mosi function. i/o fc3_rxd_sda_mosi ? flexcomm 3: usart receiver, i2c data i/o, spi master-out/slave-in data. o ct0_mat1 ? match output 1 from timer 0. o sct0_out1 ? sctimer/pwm output 1. i sct0_gpi3 ? pin input 3 to sctimer/pwm. r ? reserved. i/o emc_d[1] ? external memory in terface data [1]. pio0_4/ tms b6 c8 185 87 [2] pu; z i/o pio0_4 ? general-purpose digital input/output pin. in boundary scan mode: tms (test mode select). remark: the state of this pin at reset in conjunction with pio0_5 and pio0_6 will determine the boot source for the part or if isp handler is invoked. see the boot process chapter in um11060 for more details. i can0_rd ? receiver input for can 0. i/o fc4_sck ? flexcomm 4: usart or spi clock. i ct3_cap0 ? capture input 0 to timer 3. i sct0_gpi4 ? pin input 4 to sctimer/pwm. r ? reserved. i/o emc_d[2] ? external memory in terface data [2]. o enet_mdc ? ethernet management data clock. pio0_5/ tdi a5 e7 189 89 [2] pu; z i/o pio0_5 ? general-purpose digital input/output pin. in boundary scan mode: tdi (test data in). remark: the state of this pin at reset in conjunction with pio0_4 and pio0_6 will determine the boot source for the part or if isp handler is invoked. see the boot process chapter in um11060 for more details. o can0_td ? transmitter output for can 0. i/o fc4_rxd_sda_mosi ? flexcomm 4: usart receiver, i2c data i/o, spi master-out/slave-in data. o ct3_mat0 ? match output 0 from timer 3. i sct0_gpi5 ? pin input 5 to sctimer/pwm. r ? reserved. i/o emc_d[3] ? external memory in terface data [3]. i/o enet_mdio ? ethernet management data i/o. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 15 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_6/ tdo a4 a5 191 90 [2] pu; z i/o pio0_6 ? general-purpose digital input/output pin. in boundary scan mode: tdo (test data out). remark: the state of this pin at reset in conjunction with pio0_4 and pio0_5 will determine the boot source for the part or if isp handler is invoked. see the boot process chapter in um11060 for more details. i/o fc3_sck ? flexcomm 3: usart or spi clock. i ct3_cap1 ? capture input 1 to timer 3. o ct4_mat0 ? match output 0 from timer 4. i sct0_gpi6 ? pin input 6 to sctimer/pwm. r ? reserved. i/o emc_d[4] ? external memory in terface data [4]. i enet_rx_dv ? ethernet receive data valid. pio0_7 f9 h12 125 61 [2] pu; z i/o pio0_7 ? general-purpose digital input/output pin. i/o fc3_rts_scl_ssel1 ? flexcomm 3: usart request-to-send, i2c clo ck, spi slave select 1. o sd_clk ? sd/mmc clock. i/o fc5_sck ? flexcomm 5: usart or spi clock. i/o fc1_sck ? flexcomm 1: usart or spi clock. o pdm1_clk ? clock for pdm interface 1, for digital microphone. i/o emc_d[5] ? external memory in terface data [5]. i enet_rx_clk ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). pio0_8 e9 h10 133 64 [2] pu; z i/o pio0_8 ? general-purpose digital input/output pin. i/o fc3_ssel3 ? flexcomm 3: spi slave select 3. i/o sd_cmd ? sd/mmc card command i/o. i/o fc5_rxd_sda_mosi ? flexcomm 5: usart receiver, i2c data i/o, spi master-out/slave-in data. o swo ? serial wire debug trace output. i pdm1_data ? data for pdm interface 1 (digital microphone). i/o emc_d[6] ? external memory in terface data [6]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 16 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_9 e10 g12 136 65 [2] pu; z i/o pio0_9 ? general-purpose digital input/output pin. i/o fc3_ssel2 ? flexcomm 3: spi slave select 2. o sd_pow_en ? sd/mmc card power enable. i/o fc5_txd_scl_miso ? flexcomm 5: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. i/o sci1_io ? smartcard interface 1 data i/o. i/o emc_d[7] ? external memory in terface data [7]. pio0_10/ adc0_0 j1 p2 50 23 [4] pu; z i/o; ai pio0_10/adc0_0 ? general-purpose digital input/output pin. adc input channel 0 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc6_sck ? flexcomm 6: usart, spi, or i2s clock. i ct2_cap2 ? capture input 2 to timer 2. o ct2_mat0 ? match output 0 from timer 2. i/o fc1_txd_scl_miso ? flexcomm 1: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. o swo ? serial wire debug trace output. pio0_11/ adc0_1 k1 l3 51 24 [4] pu; z i/o; ai pio0_11/adc0_1 ? general-purpose digital input/output pin. adc input channel 1 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc6_rxd_sda_mosi_data ? flexcomm 6: usart receiver, i2c data i/o, spi ma ster-out/slave-in data, i2s data i/o. o ct2_mat2 ? match output 2 from timer 2. i freqme_gpio_clk_a ? frequency measure pin clock input a. r ? reserved. r ? reserved. i swclk ? serial wire debug clock. this is the default function after booting. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 17 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_12/ adc0_2 j2 m3 52 25 [4] pu; z i/o; ai pio0_12/adc0_2 ? general-purpose digital input/output pin. adc input channel 2 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc3_txd_scl_miso ? flexcomm 3: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. i freqme_gpio_clk_b ? frequency measure pin clock input b. i sct0_gpi7 ? pin input 7 to sctimer/pwm. r ? reserved. i/o swdio ? serial wire debug i/o. this is the default function after booting. pio0_13 c10 f11 141 67 [3] z i/o pio0_13 ? general-purpose digital input/output pin. remark: in isp mode, this pin is set to the flexcomm 1 i2c sda function. i/o fc1_cts_sda_ssel0 ? flexcomm 1: usart clear-to-send, i2c data i/o, spi slave select 0. i utick_cap0 ? micro-tick timer capture input 0. i ct0_cap0 ? capture input 0 to timer 0. i sct0_gpi0 ? pin input 0 to sctimer/pwm. r ? reserved. r ? reserved. i enet_rxd0 ? ethernet receive data 0. pio0_14 d9 e13 144 69 [3] z i/o pio0_14 ? general-purpose digita l input/output pin. remark: in isp mode, this pin is set to the flexcomm 1 i2c scl function. i/o fc1_rts_scl_ssel1 ? flexcomm 1: usart request-to-send, i2c clo ck, spi slave select 1. i utick_cap1 ? micro-tick timer capture input 1. i ct0_cap1 ? capture input 1 to timer 0. i sct0_gpi1 ? pin input 1 to sctimer/pwm. r ? reserved. r ? reserved. i enet_rxd1 ? ethernet receive data 1. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 18 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_15/ adc0_3 k2 l4 53 26 [4] pu; z i/o; ai pio0_15/adc0_3 ? general-purpose digital input/output pin. adc input channel 3 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc6_cts_sda_ssel0 ? flexcomm 6: usart clear-to-send, i2c data i/o, spi slave select 0. i utick_cap2 ? micro-tick timer capture input 2. i ct4_cap0 ? capture input 4 to timer 0. o sct0_out2 ? sctimer/pwm output 2. r ? reserved. o emc_wen ? external memory interface write enable (active low). o enet_tx_en ? ethernet transmit enable (rmii/mii interface). pio0_16/ adc0_4 h3 m4 54 27 [4] pu; z i/o; ai pio0_16/adc0_4 ? general-purpose digital input/output pin. adc input channel 4 if the digimode bit is set to 0 in the iocon register for this pin.ws i/o fc4_txd_scl_miso ? flexcomm 4: usart transmitter, i2c clock, spi master-in/slave-out data. o clkout ? output of the clkout function. i ct1_cap0 ? capture input 0 to timer 1. r ? reserved. r ? reserved. o emc_csn[0] ? external memory interface static chip select 0 (active low). o enet_txd0 ? ethernet transmit data 0. pio0_17 b10 e14 146 70 [2] pu; z i/o pio0_17 ? general-purpose digital input/output pin. i/o fc4_ssel2 ? flexcomm 4: spi slave select 2. i sd_card_det_n ? sd/mmc card detect (active low). i sct0_gpi7 ? pin input 7 to sctimer/pwm. o sct0_out0 ? sctimer/pwm output 0. r ? reserved. o emc_oen ? external memory interface output enable (active low) o enet_txd1 ? ethernet transmit data 1. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 19 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_18 c9 c14 150 72 [2] pu; z i/o pio0_18 ? general-purpose digita l input/output pin. i/o fc4_cts_sda_ssel0 ? flexcomm 4: usart clear-to-send, i2c data i/o, spi slave select 0. i sd_wr_prt ? sd/mmc write protect. o ct1_mat0 ? match output 0 from timer 1. o sct0_out1 ? sctimer/pwm output 1. o sci1_sclk ? smartcard interface 1 clock. o emc_a[0] ? external memory interface address 0. pio0_19 c5 c6 193 91 [2] pu; z i/o pio0_19 ? general-purpose digita l input/output pin. i/o fc4_rts_scl_ssel1 ? flexcomm 4: usart request-to-send, i2c clo ck, spi slave select 1. i utick_cap0 ? micro-tick timer capture input 0. o ct0_mat2 ? match output 2 from timer 0. o sct0_out2 ? sctimer/pwm output 2. r ? reserved. o emc_a[1] ? external memory interface address 1. i/o fc7_txd_scl_miso_ws ? flexcomm 7: usart transmitter, i2c clock, spi mast er-in/slave-out data i/o, i2s word-select/frame. pio0_20 c8 d13 153 74 [2] pu; z i/o pio0_20 ? general-purpose digita l input/output pin. i/o fc3_cts_sda_ssel0 ? flexcomm 3: usart clear-to-send, i2c data i/o, spi slave select 0. o ct1_mat1 ? match output 1 from timer 1. i ct3_cap3 ? capture input 3 to timer 3. i sct0_gpi2 ? pin input 2 to sctimer/pwm. i/o sci0_io ? smartcard interface 0 data i/o. o emc_a[2] ? external memory interface address 2. i/o fc7_rxd_sda_mosi_data ? flexcomm 7: usart receiver, i2c data i/o, spi ma ster-out/slave -in data, i2s data i/o. pio0_21 b9 c13 158 77 [2] pu; z i/o pio0_21 ? general-purpose digital input/output pin. i/o fc3_rts_scl_ssel1 ? flexcomm 3: usart request-to-send, i2c clo ck, spi slave select 1. i utick_cap3 ? micro-tick timer capture input 3. o ct3_mat3 ? match output 3 from timer 3. i sct0_gpi3 ? pin input 3 to sctimer/pwm. o sci0_sclk ? smartcard interface 0 clock. o emc_a[3] ? external memory interface address 3. i/o fc7_sck ? flexcomm 7: usart, spi, or i2s clock. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 20 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_22 b8 b12 163 80 [2][8] pu; z i/o pio0_22 ? general-purpose digital input/output pin. i/o fc6_txd_scl_miso_ws ? flexcomm 6: usart transmitter, i2c clock, spi mast er-in/slave-out data i/o, i2s word-select/frame. i utick_cap1 ? micro-tick timer capture input 1. i ct3_cap3 ? capture input 3 to timer 3. o sct0_out3 ? sctimer/pwm output 3. r ? reserved. r ? reserved. i usb0_vbus ? monitors the presence of usb0 bus power. pio0_23/ adc0_11 k5 n7 71 35 [4] pu; z i/o; ai pio0_23/adc0_11 ? general-purpose digital input/output pin. adc input channel 11 if the digimode bit is set to 0 in the iocon register for this pin. i/o mclk ? mclk input or output for i2s and/or digital microphone. o ct1_mat2 ? match output 2 from timer 1. o ct3_mat3 ? match output 3 from timer 3. o sct0_out4 ? sctimer/pwm output 4. i/o fc0_cts_sda_ssel0 ? flexcomm 0: usart clear-to-send, i2c data i/o, spi slave select 0. i/o spifi_csn ? spi flash interface chip select (active low). pio0_24 j5 m7 76 38 [2] pu; z i/o pio0_24 ? general-purpose digital input/output pin. i/o fc0_rxd_sda_mosi ? flexcomm 0: usart receiver, i2c data i/o, spi master-out/slave-in data. i/o sd_d[0] ? sd/mmc data 0. i ct2_cap0 ? capture input 0 to timer 2. i sct0_gpi0 ? pin input 0 to sctimer/pwm. r ? reserved. i/o spifi_io0 ? data bit 0 for the spi flash interface. pio0_25 j6 k8 83 40 [2] pu; z i/o pio0_25 ? general-purpose digital input/output pin. i/o fc0_txd_scl_miso ? flexcomm 0: usart transmitter, i2c clock, spi master-in/slave-out data. i/o sd_d[1] ? sd/mmc data 1. i ct2_cap1 ? capture input 1 to timer 2. i sct0_gpi1 ? pin input 1 to sctimer/pwm. r ? reserved. i/o spifi_io1 ? data bit 1 for the spi flash interface. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 21 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_26 h10 m13 110 56 [2] pu; z i/o pio0_26 ? general-purpose digital input/output pin. i/o fc2_rxd_sda_mosi ? flexcomm 2: usart receiver, i2c data i/o, spi master-out/slave-in data. o clkout ? output of the clkout function. i ct3_cap2 ? capture input 2 to timer 3. o sct0_out5 ? sctimer/pwm output 5. o pdm0_clk ? clock for pdm interface 0, for digital microphone. o spifi_clk ? clock output for the spi flash interface. i usb0_idvalue ? indicates to the transceiver whether connected as an a-device (usb0_id low) or b-device (usb0_id high). i/o fc0_sck ? flexcomm 0: usart or spi clock. i/o fc10_ssel0 ? flexcomm 10: spi slave select 0. pio0_27 h7 l9 87 42 [2] pu; z i/o pio0_27 ? general-purpose digital input/output pin. i/o fc2_txd_scl_miso ? flexcomm 2: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. o ct3_mat2 ? match output 2 from timer 3. o sct0_out6 ? sctimer/pwm output 6. i pdm0_data ? data for pdm interface 0 (digital microphone). i/o spifi_io3 ? data bit 3 for the spi flash interface. pio0_28 j7 m9 91 44 [2] pu; z i/o pio0_28 ? general-purpose digital input/output pin. i/o fc0_sck ? flexcomm 0: usart or spi clock. r ? reserved. i ct2_cap3 ? capture 3 input to timer 2. o sct0_out7 ? sctimer/pwm output 7. o tracedata[3] ? trace data bit 3. i/o spifi_io2 ? data bit 2 for the spi flash interface. i usb0_overcurrentn ? usb0 bus overcurrent indicator (active low). table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 22 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio0_29 b7 b13 167 82 [2] pu; z i/o pio0_29 ? general-purpose digita l input/output pin. remark: in isp mode, this pin is set to the flexcomm 0 usart rxd function. i/o fc0_rxd_sda_mosi ? flexcomm 0: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. o ct2_mat3 ? match output 3 from timer 2. o sct0_out8 ? sctimer/pwm output 8. o tracedata[2] ? trace data bit 2. pio0_30 a2 a2 200 95 [2] pu; z i/o pio0_30 ? general-purpose digital input/output pin. remark: in isp mode, this pin is set to the flexcomm 0 usart txd function. i/o fc0_txd_scl_miso ? flexcomm 0: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. o ct0_mat0 ? match output 0 from timer 0. o sct0_out9 ? sctimer/pwm output 9. o tracedata[1] ? trace data bit 1. pio0_31/ adc0_5 k3 m5 55 28 [4] pu; z i/o; ai pio0_31/adc0_5 ? general-purpose digital input/output pin. adc input channel 5 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc0_cts_sda_ssel0 ? flexcomm 0: usart clear-to-send, i2c data i/o, spi slave select 0. i/o sd_d[2] ? sd/mmc data 2. o ct0_mat1 ? match output 1 from timer 0. o sct0_out3 ? sctimer/pwm output 3. o tracedata[0] ? trace data bit 0. pio1_0/ adc0_6 j3 n3 56 29 [4] pu; z i/o; ai pio1_0/adc0_6 ? general-purpose digital input/output pin. adc input channel 6 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc0_rts_scl_ssel1 ? flexcomm 0: usart request-to-send, i2c clo ck, spi slave select 1. i/o sd_d[3] ? sd/mmc data 3. i ct0_cap2 ? capture 2 input to timer 0. i sct0_gpi4 ? pin input 4 to sctimer/pwm. o traceclk ? trace clock. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 23 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_1 j10 k12 109 55 [2] pu; z i/o pio1_1/ ? general-purpose digital input/output pin. i/o fc3_rxd_sda_mosi ? flexcomm 3: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. i ct0_cap3 ? capture 3 input to timer 0. i sct0_gpi5 ? pin input 5 to sctimer/pwm. r ? reserved. i/o fc10_mosi ? flexcomm 10: spi ma ster-out/slave-in data. i usb1_overcurrentn ? usb1 bus overcurrent indicator (active low). pio1_2 g9 l14 117 58 [2] pu; z i/o pio1_2 ? general-purpose digital input/output pin. o can0_td ? transmitter output for can0. r ? reserved. o ct0_mat3 ? match output 3 from timer0. i sct0_gpi6 ? pin input 6 to sctimer/pwm. o pdm1_clk ? clock for pdm interface 1, for digital microphone. i/o fc10_miso ? flexcomm 10: spi ma ster-in/slave-out data. o usb1_portpwrn ? usb1 vbus drive indicator (indicates vbus must be driven). pio1_3 f10 j13 120 60 [2] pu; z i/o pio1_3 ? general-purpose digital input/output pin. i can0_rd ? receiver input for can0. r ? reserved. r ? reserved. o sct0_out4 ? sctimer/pwm output 4. i pdm1_data ? data for pdm interface 1 (digital microphone). o usb0_portpwrn ? usb0 vbus drive indicator (indicates vbus must be driven). r ? reserved. i/o fc10_sck ? flexcomm 10: spi clock. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 24 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_4 c3 d4 3 3 [2] pu; z i/o pio1_4 ? general-purpose digital input/output pin. i/o fc0_sck ? flexcomm 0: usart or spi clock. i/o sd_d[0] ? sd/mmc data 0. o ct2_mat1 ? match output 1 from timer 2. o sct0_out0 ? sctimer/pwm output 0. i freqme_gpio_clk_a ? frequency measure pin clock input a. i/o emc_d[11]) ? external memory in terface data [11]. pio1_5 c2 e4 5 4 [2] pu; z i/o pio1_5 ? general-purpose digital input/output pin. i/o fc0_rxd_sda_mosi ? flexcomm 0: usart receiver, i2c data i/o, spi master-out/slave-in data. i/o sd_d[2] ? sd/mmc data 2. o ct2_mat0 ? match output 0 from timer 2. i sct0_gpi0 ? pin input 0 to sctimer/pwm. r ? reserved. o emc_a[4] ? external memory interface address 4. pio1_6 f1 g4 30 15 [2] pu; z i/o pio1_6 ? general-purpose digital input/output pin. i/o fc0_txd_scl_miso ? flexcomm 0: usart transmitter, i2c clock, spi master-in/slave-out data. i/o sd_d[3] ? sd/mmc data 3. o ct2_mat1 ? match output 1 from timer 2. i sct0_gpi3 ? pin input 3 to sctimer/pwm. r ? reserved. o emc_a[5] ? external memory interface address 5. pio1_7 h1 n1 38 18 [2] pu; z i/o pio1_7 ? general-purpose digital input/output pin. i/o fc0_rts_scl_ssel1 ? flexcomm 0: usart request-to-send, i2c clo ck, spi slave select 1. i/o sd_d[1] ? sd/mmc data 1. o ct2_mat2 ? match output 2 from timer 2. i sct0_gpi4 ? pin input 4 to sctimer/pwm. r ? reserved. o emc_a[6] ? external memory interface address 6. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 25 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_8 h5 p8 72 36 [2] pu; z i/o pio1_8 ? general-purpose digital input/output pin. i/o fc0_cts_sda_ssel0 ? flexcomm 0: usart clear-to-send, i2c data i/o, spi slave select 0. o sd_clk ? sd/mmc clock. r ? reserved. o sct0_out1 ? sctimer/pwm output 1. i/o fc4_ssel2 ? flexcomm 4: spi slave select 2. o emc_a[7] ? external memory interface address 7. pio1_9 k7 k6 78 39 [2] pu; z i/o pio1_9 ? general-purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0. i/o fc1_sck ? flexcomm 1: usart or spi clock. i ct1_cap0 ? capture 0 input to timer 1. o sct0_out2 ? sctimer/pwm output 2. i/o fc4_cts_sda_ssel0 ? flexcomm 4: usart clear-to-send, i2c data i/o, spi slave select 0. o emc_casn ? external memory interface column access strobe (active low). pio1_10 h6 n9 84 41 [2] pu; z i/o pio1_10 ? general-purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1. i/o fc1_rxd_sda_mosi ? flexcomm 1: usart receiver, i2c data i/o, spi master-out/slave-in data. o ct1_mat0 ? match output 0 from timer 1. o sct0_out3 ? sctimer/pwm output 3. r ? reserved. o emc_rasn ? external memory interface row address strobe (active low). pio1_11 b4 b4 198 94 [2][8] pu; z i/o pio1_11 ? general-purpose digital input/output pin. o enet_tx_en ? ethernet transmit enable (rmii/mii interface). i/o fc1_txd_scl_miso ? flexcomm 1: usart transmitter, i2c clock, spi master-in/slave-out data. i ct1_cap1 ? capture 1 input to timer 1. i usb0_vbus ? monitors the presence of usb0 bus power. r ? reserved. o emc_clk[0] ? external memory interface clock 0. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 26 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_12 f8 k9 128 62 [2] pu; z i/o pio1_12 ? general-purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0. i/o fc6_sck ? flexcomm 6: usart, spi, or i2s clock. o ct1_mat1 ? match output 1 from timer 1. o usb0_portpwrn ? usb0 vbus drive indicator (indicates vbus must be driven). o emc_dycsn[0] ? external memory interface sdram chip select 0 (active low). pio1_13 d10 g10 139 66 [2] pu; z i/o pio1_13 ? general-purpose digital input/output pin. i enet_rxd1 ? ethernet receive data 1. i/o fc6_rxd_sda_mosi_data ? flexcomm 6: usart receiver, i2c data i/o, spi ma ster-out/slave -in data, i2s data i/o. i ct1_cap2 ? capture 2 input to timer 1. i usb0_overcurrentn ? usb0 bus overcurrent indicator (active low). o usb0_frame ? usb0 frame toggle signal. o emc_dqm[0] ? external memory interface data mask 0. pio1_14 a9 c12 160 78 [2] pu; z i/o pio1_14 ? general-purpose digital input/output pin. i enet_rx_dv ? ethernet receive data valid. i utick_cap2 ? micro-tick timer capture input 2. o ct1_mat2 ? match output 2 from timer 1. i/o fc5_cts_sda_ssel0 ? flexcomm 5: usart clear-to-send, i2c data i/o, spi slave select 0. o usb0_ledn ? usb0-configured led indicator (active low). o emc_dqm[1] ? external memory interface data mask 0. pio1_15 c7 a11 176 84 [2] pu; z i/o pio1_15 ? general-purpose digital input/output pin. i enet_rx_clk ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). i utick_cap3 ? micro-tick timer capture input 3. i ct1_cap3 ? capture 3 input to timer 1. i/o fc5_rts_scl_ssel1 ? flexcomm 5: usart request-to-send, i2c clo ck, spi slave select 1. i/o fc4_rts_scl_ssel1 ? flexcomm 4: usart request-to-send, i2c clo ck, spi slave select 1. o emc_cke[0] ? external memory interface sdram clock enable 0. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 27 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_16 b5 b7 187 88 [2] pu; z i/o pio1_16 ? general-purpose digital input/output pin. o enet_mdc ? ethernet management data clock. i/o fc6_txd_scl_miso_ws ? flexcomm 6: usart transmitter, i2c clock, spi mast er-in/slave-out data i/o, i2s word-select/frame. o ct1_mat3 ? match output 3 from timer 1. i/o sd_cmd ? sd/mmc card command i/o. r ? reserved. o emc_a[10] ? external memory interface address 10. pio1_17 h8 n12 98 47 [2] pu; z i/o pio1_17 ? general-purpose digital input/output pin. i/o enet_mdio ? ethernet management data i/o. i/o fc8_rxd_sda_mosi ? flexcomm 8: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. o sct0_out4 ? sctimer/pwm output 4. o can1_td ? transmitter output for can 1. o emc_blsn[0] ? external memory interface byte lane select 0 (active low). pio1_18 d2 d1 15 5 [2] pu; z i/o pio1_18 ? general-purpose digital input/output pin. r ? reserved. i/o fc8_txd_scl_miso ? flexcomm 8: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. o sct0_out5 ? sctimer/pwm output 5. i can1_rd ? receiver input for can 1. o emc_blsn[1] ? external memory interface byte lane select 1 (active low). pio1_19 f3 l1 33 16 [2] pu; z i/o pio1_19 ? general-purpose digital input/output pin. i/o fc8_sck ? flexcomm 8: usart or spi clock. o sct0_out7 ? sctimer/pwm output 7. o ct3_mat1 ? match output 1 from timer 3. i sct0_gpi7 ? pin input 7 to sctimer/pwm. i/o fc4_sck ? flexcomm 4: usart or spi clock. i/o emc_d[8] ? external memory in terface data [8]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 28 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_20 g2 m1 35 17 [2] pu; z i/o pio1_20 ? general-purpose digital input/output pin. i/o fc7_rts_scl_ssel1 ? flexcomm 7: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. i ct3_cap2 ? capture 2 input to timer 3. r ? reserved. i/o fc4_txd_scl_miso ? flexcomm 4: usart transmitter, i2c clock, spi master-in/slave-out data. i/o emc_d[9] ? external memory in terface data [9]. pio1_21 k6 n8 74 37 [2] pu; z i/o pio1_21 ? general-purpose digital input/output pin. i/o fc7_cts_sda_ssel0 ? flexcomm 7: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved. o ct3_mat2 ? match output 2 from timer 3. r ? reserved. i/o fc4_rxd_sda_mosi ? flexcomm 4: usart receiver, i2c data i/o, spi master-out/slave-in data. i/o emc_d[10] ? external memory interface data [10]. pio1_22 k8 p11 89 43 [2] pu; z i/o pio1_22 ? general-purpose digital input/output pin. i/o fc8_rts_scl_ssel1 ? flexcomm 8: usart request-to-send, i2c clo ck, spi slave select 1. i/o sd_cmd ? sd/mmc card command i/o. o ct2_mat3 ? match output 3 from timer 2. i sct0_gpi5 ? pin input 5 to sctimer/pwm. i/o fc4_ssel3 ? flexcomm 4: spi slave select 3. o emc_cke[1] ? external memory interface sdram clock enable 1. pio1_23 k10 m10 97 46 [2] pu; z i/o pio1_23 ? general-purpose digital input/output pin. i/o fc2_sck ? flexcomm 2: usart or spi clock. o sct0_out0 ? sctimer/pwm output 0. r ? reserved. i/o enet_mdio ? ethernet management data i/o. i/o fc3_ssel2 ? flexcomm 3: spi slave select 2. o emc_a[11] ? external memory interface address 11. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 29 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_24 g8 n14 111 57 [2] pu; z i/o pio1_24 ? general-purpose digital input/output pin. i/o fc2_rxd_sda_mosi ? flexcomm 2: usart receiver, i2c data i/o, spi master-out/slave-in data. o sct0_out1 ? sctimer/pwm output 1. r ? reserved. r ? reserved. i/o fc3_ssel3 ? flexcomm 3: spi slave select 3. o emc_a[12] ? external memory interface address 12. pio1_25 g10 m12 119 59 [2] pu; z i/o pio1_25 ? general-purpose digital input/output pin. i/o fc2_txd_scl_miso ? flexcomm 2: usart transmitter, i2c clock, spi master-in/slave-out data. o sct0_out2 ? sctimer/pwm output 2. r ? reserved. i utick_cap0 ? micro-tick timer capture input 0. r ? reserved. o emc_a[13] ? external memory interface address 13. pio1_26 e8 j10 131 63 [2] pu; z i/o pio1_26 ? general-purpose digital input/output pin. i/o fc2_cts_sda_ssel0 ? flexcomm 2: usart clear-to-send, i2c data i/o, spi slave select 0. o sct0_out3 ? sctimer/pwm output 3. i ct0_cap3 ? capture 3 input to timer 0. i utick_cap1 ? micro-tick timer capture input 1. r ? reserved. o emc_a[8] ? external memory interface address 8. pio1_27 d8 f10 142 68 [2] pu; z i/o pio1_27 ? general-purpose digital input/output pin. i/o fc2_rts_scl_ssel1 ? flexcomm 2: usart request-to-send, i2c clo ck, spi slave select 1. i/o sd_d[4] ? sd/mmc data 4. o ct0_mat3 ? match output 3 from timer 0. o clkout ? output of the clkout function. r ? reserved. o emc_a[9] ? external memory interface address 9. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 30 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio1_28 a10 e12 151 73 [2] pu; z i/o pio1_28 ? general-purpose digital input/output pin. i/o fc7_sck ? flexcomm 7: usart, spi, or i2s clock. i/o sd_d[5] ? sd/mmc data 5. i ct0_cap2 ? capture 2 input to timer 0. r ? reserved. r ? reserved. i/o emc_d[12] ? external memory interface data [12]. pio1_29 a8 c11 165 81 [2][8] pu; z i/o pio1_29 ? general-purpose digital input/output pin. i/o fc7_rxd_sda_mosi_data ? flexcomm 7: usart receiver, i2c data i/o, spi ma ster-out/slave -in data, i2s data i/o. i/o sd_d[6] ? sd/mmc data 6. i sct0_gpi6 ? pin input 6 to sctimer/pwm. o usb1_portpwrn ? usb1 vbus drive indicator (indicates vbus must be driven). o usb1_frame ? usb1 frame toggle signal. i/o emc_d[13] ? external memory interface data [13]. pio1_30 c6 a8 182 86 [2] pu; z i/o pio1_30 ? general-purpose digital input/output pin. i/o fc7_txd_scl_miso_ws ? flexcomm 7: usart transmitter, i2c clock, spi mast er-in/slave-out data i/o, i2s word-select/frame. i/o sd_d[7] ? sd/mmc data 7. i sct0_gpi7 ? pin input 7 to sctimer/pwm. i usb1_overcurrentn ? usb1 bus overcurrent indicator (active low). o usb1_ledn ? usb1-configured led indicator (active low). i/o emc_d[14] ? external memory interface data [14]. pio1_31 a3 c5 195 92 [2] pu; z i/o pio1_31 ? general-purpose digital input/output pin. i/o mclk ? mclk input or output for i2s and/or digital microphone. r ? reserved. o ct0_mat2 ? match output 2 from timer 0. o sct0_out6 ? sctimer/pwm output 6. i/o fc8_cts_sda_ssel0 ? flexcomm 8: usart clear-to-send, i2c data i/o, spi slave select 0. i/o emc_d[15] ? external memory interface data [15]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 31 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio2_0/ adc0_7 -p357- [4] pu; z i/o; ai pio2_0/adc0_7 ? general-purpose digital input/output pin. adc input channel 7 if the digimode bit is set to 0 in the iocon register for this pin. r ? reserved. i/o fc0_rxd_sda_mosi ? flexcomm 0: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. o ct1_cap0 ? capture input 0 to timer 1. pio2_1/ adc0_8 -p458- [4] pu; z i/o; ai pio2_1/adc0_8 ? general-purpose digital input/output pin. adc input channel 8 if the digimode bit is set to 0 in the iocon register for this pin. r ? reserved. i/o fc0_txd_scl_miso ? flexcomm 0: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. o ct1_mat0 ? match output 0 from timer 1. pio2_2 - c3 4 - [2] pu; z i/o pio2_2 ? general-purpose digital input/output pin. i enet_crs ? ethernet carrier sense (mii interface) or ethernet carrier sense/data valid (rmii interface). i/o fc3_ssel3 ? flexcomm 3: spi slave select 3. o sct0_out6 ? sctimer/pwm output 6. o ct1_mat1 ? match output 1 from timer 1. pio2_3 - b1 7 - [2] pu; z i/o pio2_3 ? general-purpose digital input/output pin. o enet_txd2 ? ethernet transmit data 2 (mii interface). o sd_clk ? sd/mmc clock. i/o fc1_rxd_sda_mosi ? flexcomm 1: usart receiver, i2c data i/o, spi master-out/slave-in data. o ct2_mat0 ? match output 0 from timer 2. pio2_4 - d3 9 - [2] pu; z i/o pio2_4 ? general-purpose digital input/output pin. o enet_txd3 ? ethernet transmit data 3 (mii interface). i/o sd_cmd ? sd/mmc card command i/o. i/o fc1_txd_scl_miso ? flexcomm 1: usart transmitter, i2c clock, spi master-in/slave-out data. o ct2_mat1 ? match output 1 from timer 2. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 32 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio2_5 - c1 12 - [2] pu; z i/o pio2_5 ? general-purpose digital input/output pin. o enet_tx_er ? ethernet transmit error (mii interface). o sd_pow_en ? sd/mmc card power enable i/o fc1_cts_sda_ssel0 ? flexcomm 1: usart clear-to-send, i2c data i/o, spi slave select 0. o ct1_mat2 ? match output 2 from timer 1. pio2_6 - f3 17 - [2] pu; z i/o pio2_6 ? general-purpose digital input/output pin. i enet_tx_clk ? ethernet transmit clock (mii interface). i/o sd_d[0] ? sd/mmc data 0. i/o fc1_rts_scl_ssel1 ? flexcomm 1: usart request-to-send, i2c clo ck, spi slave select 1. i ct0_cap0 ? capture input 0 to timer 0. pio2_7 - j2 29 - [2] pu; z i/o pio2_7 ? general-purpose digital input/output pin. i enet_col ? ethernet collision detec t (mii interface). i/o sd_d(1) ? sd/mmc data 1. i freqme_gpio_clk_b ? frequency measure pin clock input b. i ct0_cap1 ? capture input 1 to timer 0. pio2_8 - f4 32 - [2] pu; z i/o pio2_8 ? general-purpose digital input/output pin. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o sd_d[2] ? sd/mmc data 2. r ? reserved. o ct0_mat0 ? match output 0 from timer 0. pio2_9 - k2 36 - [2] pu; z i/o pio2_9 ? general-purpose digital input/output pin. i enet_rxd3 ? ethernet receive data 3 (mii interface). i/o sd_d[3] ? sd/mmc data 3. r ? reserved. o ct0_mat1 ? match output 0 from timer 1. pio2_10 - p1 39 - [2] pu; z i/o pio2_10 ? general-purpose digital input/output pin. i enet_rx_er ? ethernet receive error (rmii/mii interface). i sd_card_det_n ? sd/mmc card detect (active low). pio2_11 - k3 43 - [2] pu; z i/o pio2_11 ? general-purpose digital input/output pin. o lcd_pwr ? lcd panel power enable. o sd_volt[0] ? sd/mmc card regulator voltage control [0]. r ? reserved. r ? reserved. i/o fc5_sck ? flexcomm 5: usart or spi clock. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 33 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio2_12 - m2 45 - [2] pu; z i/o pio2_12 ? general-purpose digital input/output pin. o lcd_le ? lcd line end signal. o sd_volt[1] ? sd/mmc card regulator voltage control [1]. i usb0_idvalue ? indicates to the transceiver whether connected as an a-device (usb0_id low) or b-device (usb0_id high). r ? reserved. i/o fc5_rxd_sda_mosi ? flexcomm 5: usart receiver, i2c data i/o, spi master-out/slave-in data. pio2_13 - p7 70 - [2] pu; z i/o pio2_13 ? general-purpose digital input/output pin. o lcd_dclk ? lcd panel clock. o sd_volt[2] ? sd/mmc card regulator voltage control [2]. r ? reserved. r ? reserved. i/o fc5_txd_scl_miso ? flexcomm 5: usart transmitter, i2c clock, spi master-in/slave-out data. pio2_14 - l7 77 - [2][8] pu; z i/o pio2_14 ? general-purpose digital input/output pin. o lcd_fp ? lcd frame pulse (stn). vertical synchronization pulse (tft). o usb0_frame ? usb0 frame toggle signal. o usb0_portpwrn ? usb0 vbus drive indicator (indicates vbus must be driven). o ct0_mat2 ? match output 2 from timer 0. i/o fc5_cts_sda_ssel0 ? flexcomm 5: usart clear-to-send, i2c data i/o, spi slave select 0. pio2_15 - m8 79 - [2] pu; z i/o pio2_15 ? general-purpose digital input/output pin. o lcd_ac ? lcd stn ac bias drive or tft data enable output. o usb0_ledn ? usb0-configured led indicator (active low). i usb0_overcurrentn ? usb0 bus overcurrent indicator (active low). o ct0_mat3 ? match output 3 from timer 0. i/o fc5_rts_scl_ssel1 ? flexcomm 5: usart request-to-send, i2c clo ck, spi slave select 1. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 34 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio2_16 - l8 81 - [2][8] pu; z i/o pio2_16 ? general-purpose digital input/output pin. o lcd_lp ? lcd line synchronization pulse (stn). horizontal synchronization pulse (tft). o usb1_frame ? usb1 frame toggle signal. o usb1_portpwrn ? usb1 vbus drive indicator (indicates vbus must be driven). o ct1_mat3 ? match output 3 from timer 1. i/o fc8_sck ? flexcomm 8: usart or spi clock. pio2_17 - p10 86 - [2] pu; z i/o pio2_17 ? general-purpose digital input/output pin. i lcd_clkin ? lcd clock input. o usb1_ledn ? usb1-configured led indicator (active low). i usb1_overcurrentn ? usb1 bus overcurrent indicator (active low). i ct1_cap1 ? capture 1 input to timer 1. i/o fc8_rxd_sda_mosi ? flexcomm 8: usart receiver, i2c data i/o, spi master-out/slave-in data. pio2_18 - n10 90 - [2] pu; z i/o pio2_18 ? general-purpose digital input/output pin. o lcd_vd[0] ? lcd data [0]. i/o fc3_rxd_sda_mosi ? flexcomm 3: usart receiver, i2c data i/o, spi master-out/slave-in data. i/o fc7_sck ? flexcomm 7: usart, spi, or i2s clock. o ct3_mat0 ? match output 0 from timer 3. pio2_19 - p12 93 - [2] pu; z i/o pio2_19 ? general-purpose digital input/output pin. o lcd_vd[1] ? lcd data [1]. i/o fc3_txd_scl_miso ? flexcomm 3: usart transmitter, i2c clock, spi master-in/slave-out data. i/o fc7_rxd_sda_mosi_data ? flexcomm 7: usart receiver, i2c data i/o, spi ma ster-out/slave -in data, i2s data i/o. o ct3_mat1 ? match output 1 from timer 3. pio2_20 - p13 95 - [2] pu; z i/o pio2_20 ? general-purpose digital input/output pin. o lcd_vd[2] ? lcd data [2]. i/o fc3_rts_scl_ssel1 ? flexcomm 3: usart request-to-send, i2c clo ck, spi slave select 1. i/o fc7_txd_scl_miso_ws ? flexcomm 7: usart transmitter, i2c clock, spi mast er-in/slave-out data i/o, i2s word-select/frame. o ct3_mat2 ? match output 2 from timer 3. i ct4_cap0 ? capture input 4 to timer 0. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 35 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio2_21 - l10 99 - [2] pu; z i/o pio2_21 ? general-purpose digital input/output pin. o lcd_vd[3] ? lcd data [3]. i/o fc3_cts_sda_ssel0 ? flexcomm 3: usart clear-to-send, i2c data i/o, spi slave select 0. i/o mclk ? mclk input or output for i2s and/or digital microphone. o ct3_mat3 ? match output 3 from timer 3. pio2_22 - k10 113 - [2] pu; z i/o pio2_22 ? general-purpose digital input/output pin. o lcd_vd[4] ? lcd data [4]. o sct0_out7 ? sctimer/pwm output 7. r ? reserved. i ct2_cap0 ? capture input 0 to timer 2. r ? reserved. fc10_ssel1 ? flexcomm 10: spi slave select 1. pio2_23 - m14 115 - [2] pu; z i/o pio2_23 ? general-purpose digital input/output pin. o lcd_vd[5] ? lcd data [5]. o sct0_out8 ? sctimer/pwm output 8. r ? reserved. r ? reserved. r ? reserved. i/o fc10_ssel2 ? flexcomm 10: spi slave select 2. pio2_24 - k14 118 - [2] pu; z i/o pio2_24 ? general-purpose digital input/output pin. o lcd_vd[6] ? lcd data [6]. o sct0_out9 ? sctimer/pwm output 9. r ? reserved. r ? reserved. r ? reserved. i/o fc10_ssel3 ? flexcomm 10: spi slave select 3. pio2_25 - j11 121 - [2][8] pu; z i/o pio2_25 ? general-purpose digital input/output pin. o lcd_vd[7] ? lcd data [7]. i usb0_vbus ? monitors the presence of usb0 bus power. pio2_26 - h11 124 - [2] pu; z i/o pio2_26 ? general-purpose digital input/output pin. o lcd_vd[8] ? lcd data [8]. r ? reserved. i/o fc3_sck ? flexcomm 3: usart or spi clock. i ct2_cap1 ? capture input 1 to timer 2. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 36 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio2_27 - h14 130 - [2] pu; z i/o pio2_27 ? general-purpose digital input/output pin. o lcd_vd[9] ? lcd data [9]. i/o fc9_sck ? flexcomm 9: usart or spi clock. i/o fc3_ssel2 ? flexcomm 3: spi slave select 2. pio2_28 - g13 134 - [2] pu; z i/o pio2_28 ? general-purpose digital input/output pin. o lcd_vd[10]) ? lcd data [10]. i/o fc7_cts_sda_ssel0 ? flexcomm 7: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved i ct2_cap2 ? capture input 2 to timer 2. pio2_29 - g11 137 - [2] pu; z i/o pio2_29 ? general-purpose digital input/output pin. o lcd_vd[11] ? lcd data [11]. i/o fc7_rts_scl_ssel1 ? flexcomm 7: usart request-to-send, i2c clo ck, spi slave select 1. i/o fc8_txd_scl_miso ? flexcomm 8: usart transmitter, i2c clock, spi master-in/slave-out data. i ct2_cap3 ? capture 3 input to timer 2. o clkout ? output of the clkout function. pio2_30 - f12 143 - [2] pu; z i/o pio2_30 ? general-purpose digital input/output pin. o lcd_vd[12] ? lcd data [12]. r ? reserved. r ? reserved. o ct2_mat2 ? match output 2 from timer 2. pio2_31 - d14 149 - [2] pu; z i/o pio2_31 ? general-purpose digital input/output pin. o lcd_vd[13] ? lcd data [13]. pio3_0 - d12 155 - [2] pu; z i/o pio3_0 ? general-purpose digital input/output pin. o lcd_vd[14] ? lcd data [14]. o pdm0_clk ? clock for pdm interface 0, for digital microphone. r ? reserved. o ct1_mat0 ? match output 0 from timer 1. pio3_1 - d11 159 - [2] pu; z i/o pio3_1 ? general-purpose digital input/output pin. o lcd_vd[15] ? lcd data [15]. i pdm0_data ? data for pdm interface 0 (digital microphone). r ? reserved. o ct1_mat1 ? match output 1 from timer 1. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 37 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio3_2 - c10 164 - [2] pu; z i/o pio3_2 ? general-purpose digital input/output pin. o lcd_vd[16] ? lcd data [16]. i/o fc9_rxd_sda_mosi ? flexcomm 9: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. o ct1_mat2 ? match output 2 from timer 1. pio3_3 - a13 169 - [2] pu; z i/o pio3_3 ? general-purpose digital input/output pin. o lcd_vd[17] ? lcd data [17]. i/o fc9_txd_scl_miso ? flexcomm 9: usart transmitter, i2c clock, spi master-in/slave-out data. pio3_4 - b11 172 - [2] pu; z i/o pio3_4 ? general-purpose digital input/output pin. o lcd_vd[18] ? lcd data [18]. r ? reserved. i/o fc8_cts_sda_ssel0 ? flexcomm 8: usart clear-to-send, i2c data i/o, spi slave select 0. i ct4_cap1 ? capture input 4 to timer 1. pio3_5 - b10 177 - [2] pu; z i/o pio3_5 ? general-purpose digital input/output pin. o lcd_vd[19] ? lcd data [19]. r ? reserved. i/o fc8_rts_scl_ssel1 ? flexcomm 8: usart request-to-send, i2c clo ck, spi slave select 1. o ct4_mat1 ? match output 1 from timer 4. pio3_6 - c9 180 - [2] pu; z i/o pio3_6 ? general-purpose digital input/output pin. o lcd_vd[20] ? lcd data [20]. o lcd_vd[0] ? lcd data [0]. r ? reserved. o ct4_mat2 ? match output 2 from timer 4. pio3_7 - b8 184 - [2] pu; z i/o pio3_7 ? general-purpose digital input/output pin. o lcd_vd[21] ? lcd data [21]. o lcd_vd[1] ? lcd data [1]. r ? reserved. i ct4_cap2 ? capture input 2 to timer 4. pio3_8 - a7 186 - [2] pu; z i/o pio3_8 ? general-purpose digital input/output pin. o lcd_vd[22] ? lcd data [22]. o lcd_vd[2] ? lcd data [2]. r ? reserved. i ct4_cap3 ? capture input 3 to timer 4. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 38 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio3_9 - c7 192 - [2] pu; z i/o pio3_9 ? general-purpose digital input/output pin. o lcd_vd[23] ? lcd data [23]. o lcd_vd[3] ? lcd data [3]. r ? reserved. i ct0_cap2 ? capture input 2 to timer 0. pio3_10 - a3 199 - [2] pu; z i/o pio3_10 ? general-purpose digital input/output pin. o sct0_out3 ? sctimer/pwm output 3. r ? reserved. o ct3_mat0 ? match output 0 from timer 3. r ? reserved. r ? reserved. o emc_dycsn[1] ? external memory interface sdram chip select 1(active low). o tracedata[0] ? trace data bit 0. pio3_11 - b2 208 - [2] pu; z i/o pio3_11 ? general-purpose digital input/output pin. i/o mclk ? mclk input or output for i2s and/or digital microphone. i/o fc0_sck ? flexcomm 0: usart or spi clock. i/o fc1_sck ? flexcomm 1: usart or spi clock. r ? reserved. r ? reserved. r ? reserved. o tracedata[3] ? trace data bit 3. pio3_12 - l2 37 - [2] pu; z i/o pio3_12 ? general-purpose digital input/output pin. o sct0_out8 ? sctimer/pwm output 8. r ? reserved. i ct3_cap0 ? capture input 0 to timer 3. r ? reserved. o clkout ? output of the clkout function. o emc_clk[1] ? external memory interface clock 1. o traceclk ? trace clock. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 39 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio3_13 - h4 75 - [2] pu; z i/o pio3_13 ? general-purpose digital input/output pin. o sct0_out9 ? sctimer/pwm output 9. i/o fc9_cts_sda_ssel0 ? flexcomm 9: usart clear-to-send, i2c data i/o, spi slave select 0. i ct3_cap1 ? capture input 1 to timer 3. r ? reserved. r ? reserved. i emc_fbck ? external memory interface feedback clock. o tracedata[1] ? trace data bit 1. pio3_14 - e3 13 - [2] pu; z i/o pio3_14 ? general-purpose digital input/output pin. o sct0_out4 ? sctimer/pwm output 4. i/o fc9_rts_scl_ssel1 ? flexcomm 9: usart request-to-send, i2c clo ck, spi slave select 1. o ct3_mat1 ? match output 1 from timer 3. r ? reserved. r ? reserved. r ? reserved. o tracedata[2] ? trace data bit 2. pio3_15 - d2 11 - [2] pu; z i/o pio3_15 ? general-purpose digital input/output pin. i/o fc8_sck ? flexcomm 8: usart or spi clock. i sd_wr_prt ? sd/mmc write protect. pio3_16 - e1 19 - [2] pu; z i/o pio3_16 ? general-purpose digital input/output pin. i/o fc8_rxd_sda_mosi ? flexcomm 8: usart receiver, i2c data i/o, spi master-out/slave-in data. i/o sd_d[4] ? sd/mmc data 4. pio3_17 - k1 31 - [2] pu; z i/o pio3_17 ? general-purpose digital input/output pin. i/o fc8_txd_scl_miso ? flexcomm 8: usart transmitter, i2c clock, spi master-in/slave-out data. i/o sd_d[5] ? sd/mmc data 5. pio3_18 - m6 68 - [2] pu; z i/o pio3_18 ? general-purpose digital input/output pin. i/o fc8_cts_sda_ssel0 ? flexcomm 8: usart clear-to-send, i2c data i/o, spi slave select 0. i/o sd_d[6] ? sd/mmc data 6. o ct4_mat0 ? match output 0 from timer 4. o can0_td ? transmitter output for can 0. o sct0_out5 ? sctimer/pwm output 5. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 40 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio3_19 - j3 44 - [2] pu; z i/o pio3_19 ? general-purpose digital input/output pin. i/o fc8_rts_scl_ssel1 ? flexcomm 8: usart request-to-send, i2c clo ck, spi slave select 1. i/o sd_d[7] ? sd/mmc data 7. o ct4_mat1 ? match output 1 from timer 4. i can0_rd ? receiver input for can 0. o sct0_out6 ? sctimer/pwm output 6. pio3_20 - n2 46 - [2] pu; z i/o pio3_20 ? general-purpose digital input/output pin. i/o fc9_sck ? flexcomm 9: usart or spi clock. i sd_card_int_n ? o clkout ? output of the clkout function. r ? reserved. o sct0_out7 ? sctimer/pwm output 7. pio3_21/ adc0_9 -p561- [4] pu; z i/o; ai pio3_21/adc0_9 ? general-purpose digital input/output pin. adc input channel 9 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc9_rxd_sda_mosi ? flexcomm 9: usart receiver, i2c data i/o, spi master-out/slave-in data. o sd_backend_pwr ? sd/mmc back-end power supply for embedded device. o ct4_mat3 ? match output 3 from timer 4. i utick_cap2 ? micro-tick timer capture input 2. pio3_22/ adc0_10 -n562- [4] pu; z i/o; ai pio3_22/adc0_10 ? general-purpose digital input/output pin. adc input channel 10 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc9_txd_scl_miso ? flexcomm 9: usart transmitter, i2c clock, spi master-in/slave-out data. pio3_23 - c2 8 - [3] z i/o pio3_23 ? general-purpose digital input/output pin. i/o fc2_cts_sda_ssel0 ? flexcomm 2: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved. i utick_cap3 ? micro-tick timer capture input 3. pio3_24 - e2 16 - [3] z i/o pio3_24 ? general-purpose digital input/output pin. i/o fc2_rts_scl_ssel1 ? flexcomm 2: usart request-to-send, i2c clo ck, spi slave select 1. i ct4_cap0 ? capture input 4 to timer 0. i usb0_vbus ? monitors the presence of usb0 bus power. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 41 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio3_25 - p9 82 - [2] pu; z i/o pio3_25 ? general-purpose digital input/output pin. r ? reserved. i ct4_cap2 ? capture input 2 to timer 4. i/o fc4_sck ? flexcomm 4: usart or spi clock. r ? reserved. r ? reserved. o emc_a[14] ? external memory interface address 14. pio3_26 - k5 88 - [2] pu; z i/o pio3_26 ? general-purpose digital input/output pin. r ? reserved. o sct0_out0 ? sctimer/pwm output 0. i/o fc4_rxd_sda_mosi ? flexcomm 4: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. r ? reserved. o emc_a[15] ? external memory interface address 15. pio3_27 - p14 96 - [2] pu; z i/o pio3_27 ? general-purpose digital input/output pin. r ? reserved. o sct0_out1 ? sctimer/pwm output 1. i/o fc4_txd_scl_miso ? flexcomm 4: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. r ? reserved. o emc_a[16] ? external memory interface address 16. pio3_28 - m11 100 - [2] pu; z i/o pio3_28 ? general-purpose digital input/output pin. r ? reserved. o sct0_out2 ? sctimer/pwm output 2. i/o fc4_cts_sda_ssel0 ? flexcomm 4: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved. r ? reserved. o emc_a[17] ? external memory interface address 17. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 42 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio3_29 - l13 112 - [2] pu; z i/o pio3_29 ? general-purpose digital input/output pin. r ? reserved. o sct0_out3 ? sctimer/pwm output 3. i/o fc4_rts_scl_ssel1 ? flexcomm 4: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. r ? reserved. o emc_a[18] ? external memory interface address 18. pio3_30 - k13 116 - [2] pu; z i/o pio3_30 ? general-purpose digital input/output pin. i/o fc9_cts_sda_ssel0 ? flexcomm 9: usart clear-to-send, i2c data i/o, spi slave select 0. o sct0_out4 ? sctimer/pwm output 4. i/o fc4_ssel2 ? flexcomm 4: spi slave select 2. r ? reserved. r ? reserved. o emc_a[19] ? external memory interface address 19. pio3_31 - j14 123 - [2] pu; z i/o pio3_31 ? general-purpose digital input/output pin. i/o fc9_rts_scl_ssel1 ? flexcomm 9: usart request-to-send, i2c clo ck, spi slave select 1. o sct0_out5 ? sctimer/pwm output 5. o ct4_mat2 ? match output 2 from timer 4. r ? reserved. i sct0_gpi0 ? pin input 0 to sctimer/pwm. o emc_a[20] ? external memory interface address 20. pio4_0 - h13 127 - [2] pu; z i/o pio4_0 ? general-purpose digital input/output pin. r ? reserved. i/o fc6_cts_sda_ssel0 ? flexcomm 6: usart clear-to-send, i2c data i/o, spi slave select 0. i ct4_cap1 ? capture input 4 to timer 1. r ? reserved. i sct0_gpi1 ? pin input 1 to sctimer/pwm. o emc_csn[1] ? external memory interface static chip select 1(active low). table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 43 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_1 - g14 132 - [2] pu; z i/o pio4_1 ? general-purpose digital input/output pin. r ? reserved. i/o fc6_sck ? flexcomm 6: usart, spi, or i2s clock. r ? reserved. r ? reserved. i sct0_gpi2 ? pin input 2 to sctimer/pwm. o emc_csn[2] ? external memory interface static chip select 2 (active low). pio4_2 - f14 138 - [2] pu; z i/o pio4_2 ? general-purpose digital input/output pin. r ? reserved. i/o fc6_rxd_sda_mosi_data ? flexcomm 6: usart receiver, i2c data i/o, spi ma ster-out/slave-in data, i2s data i/o. r ? reserved. r ? reserved. i sct0_gpi3 ? pin input 3 to sctimer/pwm. o emc_csn[3] ? external memory interface static chip select 3 (active low). pio4_3 - f13 140 - [2] pu; z i/o pio4_3 ? general-purpose digital input/output pin. r ? reserved. i/o fc6_txd_scl_miso_ws ? flexcomm 6: usart transmitter, i2c clock, spi mast er-in/slave-out data i/o, i2s word-select/frame. i ct0_cap3 ? capture 3 input to timer 0. r ? reserved. i sct0_gpi4 ? pin input 4 to sctimer/pwm. o emc_dycsn[2] ? external memory interface sdram chip select 2 (active low). pio4_4 - d9 147 - [2] pu; z i/o pio4_4 ? general-purpose digital input/output pin. r ? reserved. i/o fc4_ssel3 ? flexcomm 4: spi slave select 3. i/o fc0_rts_scl_ssel1 ? flexcomm 0: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. i sct0_gpi5 ? pin input 5 to sctimer/pwm. o emc_dycsn[3] ? external memory interface sdram chip select 3 (active low). table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 44 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_5 - e10 154 - [2] pu; z i/o pio4_5 ? general-purpose digital input/output pin. r ? reserved. i/o fc9_cts_sda_ssel0 ? flexcomm 9: usart clear-to-send, i2c data i/o, spi slave select 0. i/o fc0_cts_sda_ssel0 ? flexcomm 0: usart clear-to-send, i2c data i/o, spi slave select 0. o ct4_mat3 ? match output 3 from timer 4. i sct0_gpi6 ? pin input 6 to sctimer/pwm. o emc_cke[2] ? external memory interface sdram clock enable 2. pio4_6 - d10 161 - [2] pu; z i/o pio4_6 ? general-purpose digital input/output pin. r ? reserved. i/o fc9_rts_scl_ssel1 ? flexcomm 9: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. r ? reserved. i sct0_gpi7 ? pin input 7 to sctimer/pwm. o emc_cke[3] ? external memory interface sdram clock enable 3. pio4_7 - a14 166 - [2][8] pu; z i/o pio4_7 ? general-purpose digital input/output pin. r ? reserved. i ct4_cap3 ? capture input 3 to timer 4. o usb0_portpwrn ? usb0 vbus drive indicator (indicates vbus must be driven). o usb0_frame ? usb0 frame toggle signal. i sct0_gpi0 ? pin input 0 to sctimer/pwm. pio4_8 - b14 170 - [2] pu; z i/o pio4_8 ? general-purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0. i/o fc2_sck ? flexcomm 2: usart or spi clock. i usb0_overcurrentn ? usb0 bus overcurrent indicator (active low). o usb0_ledn ? usb0-configured led indicator (active low). i sct0_gpi1 ? pin input 1 to sctimer/pwm. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 45 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_9 - a12 173 - [2][8] pu; z i/o pio4_9 ? general-purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1. i/o fc2_rxd_sda_mosi ? flexcomm 2: usart receiver, i2c data i/o, spi master-out/slave-in data. o usb1_portpwrn ? usb1 vbus drive indicator (indicates vbus must be driven). o usb1_frame ? usb1 frame toggle signal. i sct0_gpi2 ? pin input 2 to sctimer/pwm. pio4_10 - b9 181 - [2] pu; z i/o pio4_10 ? general-purpose digital input/output pin. i enet_rx_dv ? ethernet receive data valid. i/o fc2_txd_scl_miso ? flexcomm 2: usart transmitter, i2c clock, spi master-in/slave-out data. i usb1_overcurrentn ? usb1 bus overcurrent indicator (active low). o usb1_ledn ? usb1-configured led indicator (active low). sct0_gpi3 ? pin input 3 to sctimer/pwm. pio4_11 - a9 183 - [2] pu; z i/o pio4_11 ? general-purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0. i/o fc2_cts_sda_ssel0 ? flexcomm 2: usart clear-to-send, i2c data i/o, spi slave select 0. i usb0_idvalue ? indicates to the transceiver whether connected as an a-device (usb0_id low) or b-device (usb0_id high). r ? reserved. i sct0_gpi4 ? pin input 4 to sctimer/pwm. pio4_12 - a6 188 - [2] pu; z i/o pio4_12 ? general-purpose digital input/output pin. i enet_rxd1 ? ethernet receive data 1. i/o fc2_rts_scl_ssel1 ? flexcomm 2: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. i sct0_gpi5 ? pin input 5 to sctimer/pwm. pio4_13 - b6 190 - [2] pu; z i/o pio4_13 ? general-purpose digital input/output pin. o enet_tx_en ? ethernet transmit enable (rmii/mii interface). o ct4_mat0 ? match output 0 from timer 4. r ? reserved. i sct0_gpi6 ? pin input 6 to sctimer/pwm. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 46 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_14 - b5 194 - [2] pu; z i/o pio4_14 ? general-purpose digital input/output pin. i enet_rx_clk ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). o ct4_mat1 ? match output 1 from timer 4. i/o fc9_sck ? flexcomm 9: usart or spi clock. r ? reserved. i sct0_gpi7 ? pin input 7 to sctimer/pwm. pio4_15 - a4 197 - [2] pu; z i/o pio4_15 ? general-purpose digital input/output pin. o enet_mdc ? ethernet management data clock. o ct4_mat2 ? match output 2 from timer 4. i/o fc9_rxd_sda_mosi ? flexcomm 9: usart receiver, i2c data i/o, spi master-out/slave-in data. pio4_16 - c4 203 - [2] pu; z i/o pio4_16 ? general-purpose digital input/output pin. i/o enet_mdio ? ethernet management data i/o. o ct4_mat3 ? match output 3 from timer 4. i/o fc9_txd_scl_miso ? flexcomm 9: usart transmitter, i2c clock, spi master-in/slave-out data. pio4_17 - - 6 - [2] pu; z i/o pio4_17 ? general-purpose digital input/output pin. r ? reserved. o can1_td ? transmitter output for can 1. i ct1_cap2 ? capture 2 input to timer 1. i utick_cap0 ? micro-tick timer capture input 0. r ? reserved. o emc_blsn[2] ? external memory interface byte lane select 2 (active low). pio4_18 - - 10 - [2] pu; z i/o pio4_18 ? general-purpose digital input/output pin. r ? reserved. i can1_rd ? receiver input for can 1. i ct1_cap3 ? capture 3 input to timer 1. i utick_cap1 ? micro-tick timer capture input 1. r ? reserved. o emc_blsn[3] ? external memory interface byte lane select 3 (active low). table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 47 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_19 - - 14 - [2] pu; z i/o pio4_19 ? general-purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0. o sd_clk ? sd/mmc clock. i/o fc2_sck ? flexcomm 2: usart or spi clock. i ct4_cap2 ? capture input 2 to timer 4. r ? reserved. o emc_dqm[2] ? external memory interface data mask 2. pio4_20 - - 18 - [2] pu; z i/o pio4_20 ? general-purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1. i/o sd_cmd ? sd/mmc card command i/o. i/o fc2_rxd_sda_mosi ? flexcomm 2: usart receiver, i2c data i/o, spi master-out/slave-in data. i ct4_cap3 ? capture input 3 to timer 4. r ? reserved. o emc_dqm[3] ? external memory interface data mask 3. pio4_21 - - 34 - [2] pu; z i/o pio4_21 ? general-purpose digital input/output pin. o enet_txd2 ? ethernet transmit data 2 (mii interface). o sd_pow_en ? sd/mmc card power enable. i/o fc2_txd_scl_miso ? flexcomm 2: usart transmitter, i2c clock, spi master-in/slave-out data. o ct2_mat3 ? match output 3 from timer 2. r ? reserved. i/o emc_d[16] ? external memory interface data [16]. pio4_22 - - 47 - [2] pu; z i/o pio4_22 ? general-purpose digital input/output pin. o enet_txd3 ? ethernet transmit data 3 (mii interface). i sd_card_det_n ? sd/mmc card detect (active low). i/o fc2_rts_scl_ssel1 ? flexcomm 2: usart request-to-send, i2c clo ck, spi slave select 1. o ct1_mat3 ? match output 3 from timer 1. r ? reserved. i/o emc_d[17] ? external memory interface data [17]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 48 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_23 - - 42 - [2] pu; z i/o pio4_23 ? general-purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0. i sd_wr_prt ? sd/mmc write protect. i/o fc2_cts_sda_ssel0 ? flexcomm 2: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved. o ct1_mat0 ? match output 0 from timer 1. i/o emc_d[18] ? external memory interface data [18]. pio4_24 - - 67 - [2] pu; z i/o pio4_24 ? general-purpose digital input/output pin. i enet_rxd1 ? ethernet receive data 1. i sd_card_int_n ? card interrupt line. i/o fc7_rts_scl_ssel1 ? flexcomm 7: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. o ct1_mat1 ? match output 1 from timer 1. i/o emc_d[19] ? external memory interface data [19]. pio4_25 - - 69 - [2] pu; z i/o pio4_25 ? general-purpose digital input/output pin. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o sd_d[0] ? sd/mmc data 0. i/o fc7_cts_sda_ssel0 ? flexcomm 7: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved. o ct1_mat2 ? match output 2 from timer 1. i/o emc_d[20] ? external memory interface data [20]. pio4_26 - - 73 - [2] pu; z i/o pio4_26 ? general-purpose digital input/output pin. i enet_rxd3 ? ethernet receive data 3 (mii interface). i/o sd_d[1] ? sd/mmc data 1. r ? reserved. i utick_cap2 ? micro-tick timer capture input 2. o ct1_mat3 ? match output 3 from timer 1. i/o emc_d[21] ? external memory interface data [21]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 49 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_27 - - 85 - [2] pu; z i/o pio4_27 ? general-purpose digital input/output pin. o enet_tx_en ? ethernet transmit enable (rmii/mii interface). i/o sd_d[2] ? sd/mmc data 2. r ? reserved. i/o fc1_sck ? flexcomm 1: usart or spi clock. i ct1_cap0 ? capture input 0 to timer 1. i/o emc_d[22] ? external memory interface data [22]. pio4_28 - - 92 - [2] pu; z i/o pio4_28 ? general-purpose digital input/output pin. o enet_tx_er ? ethernet transmit error (mii interface). i/o sd_d[3] ? sd/mmc data 3. r ? reserved. i/o fc1_rxd_sda_mosi ? flexcomm 1: usart receiver, i2c data i/o, spi master-out/slave-in data. i ct1_cap1 ? capture 1 input to timer 1. i/o emc_d[23] ? external memory interface data [23]. pio4_29 - - 102 - [2] pu; z i/o pio4_29 ? general-purpose digital input/output pin. i enet_rx_er ? ethernet receive error (rmii/mii interface). i/o sd_d[4] ? sd/mmc data 4. r ? reserved. i/o fc1_txd_scl_miso ? flexcomm 1: usart transmitter, i2c clock, spi master-in/slave-out data. i ct1_cap2 ? capture 2 input to timer 1. i/o emc_d[24] ? external memory interface data [24]. pio4_30 - - 80 - [2] pu; z i/o pio4_30 ? general-purpose digital input/output pin. i enet_tx_clk ? ethernet transmit clock (mii interface). i/o sd_d[5] ? sd/mmc data 5. o ct3_mat0 ? match output 0 from timer 3. i/o fc1_rts_scl_ssel1 ? flexcomm 1: usart request-to-send, i2c clo ck, spi slave select 1. i ct1_cap3 ? capture 3 input to timer 1. i/o emc_d[25] ? external memory interface data [25]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 50 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio4_31 - - 114 - [2] pu; z i/o pio4_31 ? general-purpose digital input/output pin. i enet_rx_clk ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). i/o sd_d[6] ? sd/mmc data 6. o ct3_mat1 ? match output 1 from timer 3. i/o fc4_sck ? flexcomm 4: usart or spi clock. r ? reserved. i/o emc_d[26] ? external memory interface data [26]. pio5_0 - - 122 - [2] pu; z i/o pio5_0 ? general-purpose digital input/output pin. i enet_rx_dv ? ethernet receive data valid. i/o sd_d[7] ? sd/mmc data 7. o ct3_mat2 ? match output 2 from timer 3. i/o fc4_rxd_sda_mosi ? flexcomm 4: usart receiver, i2c data i/o, spi master-out/slave-in data. r ? reserved. i/o emc_d[27] ? external memory interface data [27]. pio5_1 - - 126 - [2] pu; z i/o pio5_1 ? general-purpose digital input/output pin. i enet_crs ? ethernet carrier sense (mii interface) or ethernet carrier sense/data valid (rmii interface). o sd_volt[0] ? sd/mmc card regulator voltage control [0]. o ct3_mat3 ? match output 3 from timer 3. i/o fc4_txd_scl_miso ? flexcomm 4: usart transmitter, i2c clock, spi master-in/slave-out data. r ? reserved. i/o emc_d[28] ? external memory interface data [28]. pio5_2 - - 202 - [2] pu; z i/o pio5_2 ? general-purpose digital input/output pin. i enet_col ? ethernet collision detec t (mii interface). o sd_volt[1] ? sd/mmc card regulator voltage control [1]. i ct3_cap0 ? capture input 0 to timer 3. i/o fc4_cts_sda_ssel0 ? flexcomm 4: usart clear-to-send, i2c data i/o, spi slave select 0. r ? reserved. i/o emc_d[29] ? external memory interface data [29]. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 51 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio5_3 - - 129 - [2] pu; z i/o pio5_3 ? general-purpose digital input/output pin. o enet_mdc ? ethernet management data clock. o sd_volt[2] ? sd/mmc card regulator voltage control [2]. i ct3_cap1 ? capture input 1 to timer 3. i/o fc4_rts_scl_ssel1 ? flexcomm 4: usart request-to-send, i2c clo ck, spi slave select 1. r ? reserved. i/o emc_d[30] ? external memory interface data [30]. pio5_4 - - 135 - [2] pu; z i/o pio5_4 ? general-purpose digital input/output pin. i/o enet_mdio ? ethernet management data i/o. o sd_backend_pwr ? sd/mmc back-end power supply for embedded device. i ct3_cap2 ? capture input 2 to timer 3. i/o fc4_ssel2 ? flexcomm 4: spi slave select 2. r ? reserved. i/o emc_d[31] ? external memory interface data [31]. pio5_5 - - 145 - [2] pu; z i/o pio5_5 ? general-purpose digital input/output pin. i sct0_gpi0 ? pin input 0 to sctimer/pwm. o pdm1_clk ? clock for pdm interface 1, for digital microphone. i ct3_cap3 ? capture input 3 to timer 3. i/o fc4_ssel3 ? flexcomm 4: spi slave select 3. o traceclk ? trace clock. o emc_a[21] ? external memory interface address 21. pio5_6 - - 152 - [2] pu; z i/o pio5_6 ? general-purpose digital input/output pin. i sct0_gpi1 ? pin input 1 to sctimer/pwm. i pdm1_data ? data for pdm interface 1 (digital microphone). i/o fc5_sck ? flexcomm 5: usart or spi clock. o sct0_out5 ? sctimer/pwm output 5. o tracedata[0] ? trace data bit 0. o emc_a[22] ? external memory interface address 22. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 52 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller pio5_7 - - 171 - [2] pu; z i/o pio5_7 ? general-purpose digital input/output pin. i sct0_gpi2 ? pin input 2 to sctimer/pwm. i/o mclk ? mclk input or output for i2s and/or digital microphone. i/o fc5_rxd_sda_mosi ? flexcomm 5: usart receiver, i2c data i/o, spi master-out/slave-in data. o sct0_out6 ? sctimer/pwm output 6. o tracedata[1] ? trace data bit 1. o emc_a[23] ? external memory interface address 23. pio5_8 - - 175 - [2] pu; z i/o pio5_8 ? general-purpose digital input/output pin. i sct0_gpi3 ? pin input 3 to sctimer/pwm. o pdm0_clk ? clock for pdm interface 0, for digital microphone. i/o fc5_txd_scl_miso ? flexcomm 5: usart transmitter, i2c clock, spi master-in/slave-out data. o sct0_out7 ? sctimer/pwm output 7. o tracedata[2] ? trace data bit 2. o emc_a[24] ? external memory interface address 24. pio5_9 - - 179 - [2] pu; z i/o pio5_9 ? general-purpose digital input/output pin. i sct0_gpi4 ? pin input 4 to sctimer/pwm. i pdm0_data ? data for pdm interface 0 (digital microphone). i/o fc5_cts_sda_ssel0 ? flexcomm 5: usart clear-to-send, i2c data i/o, spi slave select 0. o sct0_out8 ? sctimer/pwm output 8. o tracedata[3] ? trace data bit 3. o emc_a[25] ? external memory interface address 25. pio5_10 - - 168 - [2] pu; z i/o pio5_10 ? general-purpose digital input/output pin. i sct0_gpi5 ? pin input 5 to sctimer/pwm. r ? reserved. i/o fc5_rts_scl_ssel1 ? flexcomm 5: usart request-to-send, i2c clo ck, spi slave select 1. o sct0_out9 ? sctimer/pwm output 9. i utick_cap3 ? micro-tick timer capture input 3. usb1_avssc d1 f2 20 6 usb1 analog 3.3 v ground. usb1_rext b1 f1 21 7 usb1 analog signal for reference resistor, 12.4 k ? +/-1% usb1_id c1 g1 22 8 indicates to the transceiver whether connected as an a-device (usb1_id low) or b-device (usb1_id high). usb1_vbus d3 g2 23 9 [6][8] i/o vbus pin (power on usb cable). table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 53 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller usb1_avddc3v3 e1 g3 24 10 usb1 analog 3.3 v supply. usb1_avddtx3v3 e2 h1 25 11 usb1 analog 3.3 v supply for line drivers. usb1_dp f2 h3 27 13 [6] i/o usb1 bidirectional d+ line. usb1_dm e3 h2 26 12 [6] i/o usb1 bidirectional d- line. usb1_avsstx3v3 g1 j1 28 14 usb1 anal og ground for line drivers. usb0_dp b3 e5 204 97 [6] i/o usb0 bidirectional d+ line. usb0_dm b2 d5 205 98 [6] i/o usb0 bidirectional d- line. resetn j8 n13 101 48 [5] external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and the boot code to ex ecute. wakes up the part from deep power-down mode. vdd d5; d7; e4; e6; f5; f7; g4; g6 e6; e8; f5; g5; j12; l6; l11 1; 48; 65; 104; 108; 156; 157; 206 1; 21; 33; 50; 54; 75; 76; 99 - - single 1.71 v to 3.6 v power supply powers internal digital functions and i/os. vss d4; d6; e5; e7; f4; f6; g5; g7 b3; d7; d8; e11; h5; j5; k7 2; 49; 66; 103; 107; 148; 162; 201 2; 22; 34; 49; 53; 71; 79; 96 - - ground. vdda j4 n6 64 32 - - analog supply voltage. vrefn - n4 59 - - - adc negative reference voltage. on tfbga100 and lqfp100 packages, the adc negative reference voltage is internally tied to the vssa pin. vrefp k4 p6 63 31 - - adc positive reference voltage. vssa h4 l5 60 30 - - analog ground. on tfbga100 and lq fp100 packages, the adc negative reference voltage is internally tied to the vssa pin. xtalin h2 k4 41 20 [7] - - main oscillator input. xtalout g3 j4 40 19 [7] - - main oscillator output. vbat k9 n11 94 45 - - battery supply voltage. if no battery is used, tie vbat to vdd or to ground. rtcxin j9 l12 105 51 - - rtc oscillator input. rtcxout h9 k11 106 52 - - rtc oscillator output. table 4. pin description ?continued symbol 100-pin, tfbga 180-pin, tfbga 208-pin, lqfp 100-pin, lqfp reset state [1] [9] type description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 54 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] pu = input mode, pull-up enabled ( pull-up resistor pulls up pin to v dd ). z = high impedance; pull-up or pull-down disabled, ai = analog input, i = input, o = output, f = floating. reset state reflects the pin state at reset without boot code operation. for pin st ates in the different power modes, see section 6.2.2 ? pin states in different power modes ? . for termination on unused pins, see section 6.2.1 ? termination of unused pins ? . [2] 5 v tolerant pad with programmable glitch filter (5 v tolerant if v dd present; if v dd not present, do not exceed 3.6 v); provides digital i/o functions with ttl levels and hyster esis; normal drive strength. see figure 45 . pulse width of spikes or glitches suppressed by input filter is from 3 ns to 16 ns (simulated value). [3] true open-drain pin. i2c-bus pins compliant with the i2c-bus specification for i2c standard mode, i2c fast-mode, and i2c fas t-mode plus. the pin requires an external pull-up to provide output functionality. when powe r is switched off, this pin is floating an d does not disturb the i2c lines. open-drain configurat ion applies to all functions on this pin. [4] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog input . when configured as an analog input, the digital section of t he pin is disabled, and the pin is not 5 v tolerant. [5] reset pad.5 v tolerant pad with glitch filter with hysteresis. pulse width of spikes or glitches suppressed by input filter is from 3 ns to 20 ns (simulated value) [6] 5 v tolerant transparent analog pad. [7] the oscillator input pin (xtalin) cannot be driven by an external clock. must connect a crystal between xtalin and xtalout. [8] vbus must be connected to supply voltage when using the usb peripheral. [9] for initial device revision 0a (boot ro m version 21.0), pu = input mode, pull-up enabled (pull-up resistor pulls up pin to v dd). for future device revision 1b (boot rom versi on 21.1), z = high impedance; pull-up or pull-do wn disabled. see the errata sheet lpc5 40xx (iocon.1) for more details. for future device revision 1b (boot rom version 21.1), gpio pins pi o0_12, pio0_11, pio0_2, pio0_3, pio0_4, pio0_5, and pio0_6 have the input buffer enabled (digimode, bit 8 is enabled in iocon register) and will be floating by default. if unused, it is recommended to external ly terminate this pins to prevent leakage. 6.2.1 termination of unused pins ta b l e 5 shows how to terminate pins that are not used in the application. in many cases, unused pins should be connect ed externally or configured correctly by software to minimize the overall power consumption of the part. unused pins with gpio function should be configured as outputs set to low with their internal pull-up disabled. to configure a gpio pin as output and drive it low, select the gpio function in the iocon register, select ou tput in the gpio dir register, and write a 0 to the gpio port register for that pin. di sable the pull-up in the pin?s iocon register. in addition, it is recommended to configure all gpio pins that are not bonded out on smaller packages as outputs driven low with their internal pull-up disabled. table 5. termination of unused pins pin default state [1][2] recommended termination of unused pins reset i; pu the reset pin can be left unconnected if the application does not use it. all pion_m (not open-drain) i; pu; z can be left unconnec ted if driven low and configur ed as gpio output with pull-up disabled by software. pion_m (i2c open-drain) ia can be le ft unconnected if driven low a nd configured as gpio output by software. rtcxin - connect to ground. when grounded, the rtc oscillator is disabled. rtcxout - can be left unconnected. xtalin - connect to ground. when grounded, the rtc oscillator is disabled. xtalout - can be left unconnected. vrefp - tie to vdd. vrefn - tie to vss. vdda - tie to vdd. vssa - tie to vss.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 55 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] i = input, ia = inactive (no pull-up/pull -down enabled), pu = pull-up enabled, f = floating [2] for initial device revision 0a (boot ro m version 21.0), pu = input mode, pull-up enabled (pull-up resistor pulls up pin to v dd). for future device revision 1b (boot rom versi on 21.1), z = high impedance; pull-up or pull-do wn disabled. see the errata sheet lpc5 40xx (iocon.1) for more details. for future device revision 1b (boot rom version 21.1), gpio pins pi o0_12, pio0_11, pio0_2, pio0_3, pio0_4, pio0_5, and pio0_6 have the input buffer enabled (digimode, bit 8 is enabled in iocon register) and will be floating by default. if unused, it is recommended to external ly terminate this pins to prevent leakage. 6.2.2 pin states in different power modes [1] default and programmed pin states are retained in sleep and deep-sleep. [2] for initial device revision 0a (boot ro m version 21.0), pu = input mode, pull-up enabled (pull-up resistor pulls up pin to v dd). for future device revision 1b (boot rom versi on 21.1), z = high impedance; pull-up or pull-do wn disabled. see the errata sheet lpc5 40xx (iocon.1) for more details. for future device revision 1b (boot rom version 21.1), gpio pins pi o0_12, pio0_11, pio0_2, pio0_3, pio0_4, pio0_5, and pio0_6 have the input buffer enabled (digimode, bit 8 is enabled in iocon register) and will be floating by default. if unused, it is recommended to external ly terminate this pins to prevent leakage. [3] if vbat> vdd, the external reset pin must be floating to prevent high vbat leakage. vbat - tie to vdd. usbn_dp f can be left unconnected. if usb interf ace is not used, pin can be left unconnected except in deep power-down mode where it must be externally pulled low. when the usb phy is disabled, the pins are floating. usbn_dm f can be left unconnected. if usb inte rface is not used, pin can be left unconnected except in deep power-down mode where it must be externally pulled low. when the usb phy is disabled, the pins are floating. usb1_avscc f tie to vss. usb1_vbus f tie to vdd. usb1_avddc3v3 f tie to vdd. usb1_avddtx3v3 f tie to vdd. usb1_avsstx3v3 f tie to vss. usb1_id f can be left unconnected. if usb inte rface is not used, pin can be left unconnected. table 5. termination of unused pins pin default state [1][2] recommended termination of unused pins table 6. pin states in different power modes pin active sleep deep-sleep deep power-down [3] pion_m pins (not i2c) as configured in the iocon [1] . default: internal pull-up enabled or high z [2] . floating pio0_13 to pio0_14 (open-drain i2c-bus pins) as configured in the iocon [1] . floating pio3_23 to pio3_24 (open-drain i2c-bus pins) as configured in the iocon [1] . floating reset reset function enabled. default: input, internal pull-up enabled. reset functi on disabled.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 56 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7. functional description 7.1 architectural overview the arm cortex-m4 includes th ree ahb-lite buses: the system bus, the i-code bus, and the d-code bus. the i-code and d-code core buses allow for concurrent code and data accesses from different slave ports. the lpc540xx uses a multi-layer ahb matrix to connect the arm cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters. 7.2 arm cortex-m4 processor the arm cortex-m4 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumptio n. the arm cortex-m4 offers many new features, including a thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. a 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. 7.3 arm cortex-m4 integrated floating point unit (fpu) the fpu fully supports single-precision add , subtract, multiply, divide, multiply and accumulate, and square root operations. it also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. the fpu provides floating-point computation functionality that is compliant with the ansi/ieee std 754-2008, ieee st andard for binary fl oating-point arithmetic, referred to as the ieee 754 standard. 7.4 memory protection unit (mpu) the cortex-m4 includes a memory protection unit (mpu) which can be used to improve the reliability of an embedded system by pr otecting critical data within the user application. the mpu allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses th at could potentially break the system. the mpu separates the memory into distinct regions and implements protection by preventing disallowed accesses. the mpu supports up to eight regions each of which can be divided into eight subregions. accesses to memory locations that are not defined in the mpu regions, or not permitted by the region setting, will cause the memo ry management fault exception to take place.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 57 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.5 nested vectored interrupt c ontroller (nvic) for cortex-m4 the nvic is an integral part of the cortex-m 4. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 features ? controls system exceptions and peripheral interrupts. ? supports up to 54 vectored interrupts. ? eight programmable interrupt priority leve ls, with hardware priority level masking. ? relocatable vector table. ? non-maskable interrupt (nmi). ? software interr upt generation. 7.5.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. 7.6 system tick timer (systick) the arm cortex-m4 includes a system tick time r (systick) that is intended to generate a dedicated systick exception. the clock sour ce for the systick can be the fro or the cortex-m4 core clock. 7.7 on-chip static ram the lpc540xx support 360 kb sram with se parate bus master access for higher throughput and individual power control for low-power operation. 7.8 on-chip rom the 64 kb on-chip rom contains the boot loader and the following application programming interfaces (api): ? in-application programming (iap) and in-system programming (isp). ? rom-based usb drivers (hid, cdc, msc, and dfu). ? supports serial interface booting (uart, i2c, spi) from an application processor, automated booting from nor flash (quad spif i, 8/16/32-bit external parallel flash), and usb booting (full-speed, high speed). ? execute in place (xip) from spifi nor flash (in quad, dual spifi mode or single-bit spi mode), and parallel nor flash. ? fro api for selecting fro output frequency. ? otp api for programming otp memory. ? random number generator (rng) api.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 58 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.9 memory mapping the lpc540xx incorporates several distinct me mory regions. the apb peripheral area is 512 kb in size and is divided to allow for up to 32 peripherals.each peripheral is allocated 4 kb of space simplifying the address decoding. the registers incorporated into the cpu, such as nvic, systick, and sleep mode control, are located on the private peripheral bus. the arm cortex-m4 processor has a single 4 gb address space. the following table shows how this space is used on the lpc540xx. table 7. memory usage and details address range general use address range details and description 0x0000 0000 to 0x1fff ffff sramx 0x0000 0000 - 0x0002 ffff i&d sram bank (192 kb). boot rom 0x0300 0000 - 0x0300 ffff boot rom with api services in a 64 kb space. spi flash interface (spifi) 0x1000 0000 - 0x17ff ffff spifi memory mapped access space (128 mb). 0x2000 0000 to 0x3fff ffff main sram banks 0x2000 0000 - 0x2002 7fff sram0, sram1, sram2, sram3 banks (total 160 kb). sram bit band alias addressing 0x2200 0000 - 0x23ff ffff sram bit band alias addressing (32 mb). sram bank 0x4010 0000 0x4010 2000 usb sram (8 kb). 0x4000 0000 to 0x7fff ffff apb peripherals 0x4000 0000 - 0x4001 ffff apb slave group 0 up to 32 peripheral blocks of 4 kb each (128 kb). 0x4002 0000 - 0x4003 ffff apb slave group 1 up to 32 peripheral blocks of 4 kb each (128 kb). 0x4004 0000 - 0x4005 ffff apb asynch ronous slave group 2 up to 32 peripheral blocks of 4 kb each (128 kb). ahb peripherals 0x4008 0000 - 0x400b ffff ahb peripherals (256 kb). peripheral bit band alias addressing 0x4200 0000 - 0x43ff ffff peripheral bit band alias addressing (32 mb).
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 59 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] can be up to 256 mb, upper address 0x8fff ffff, if the address shift mode is enabled. see the emcsysctrl register bit 0 in the lpc540xx user manual . [2] can be up to 128 mb, upper address 0x97ff ffff, if the address shift mode is enabled. see the emcsysctrl register bit 0 in the lpc540xx user manual . figure 9 shows the overall map of the entire address space from the user program viewpoint following reset. 0x8000 0000 to 0xdfff ffff off-chip memory via the external memory controller four static memory chip selects: 0x8000 0000 - 0x83ff ffff static memory chip select 0 (up to 64 mb) [1] 0x8800 0000 - 0x8bff ffff static memory chip select 1 (up to 64 mb) [2] 0x9000 0000 ? 0x93ff ffff static memory chip select 2 (up to 64 mb). 0x9800 0000 - 0x9bff ffff static memory chip select 3 (up to 64 mb). four dynamic memory chip selects: 0xa000 0000 - 0xa7ff ffff dynamic memory chip select 0 (up to 256 mb). 0xa800 0000 - 0xafff ffff dynamic memory chip select 1 (up to 256 mb). 0xb000 0000 - 0xb7ff ffff dynamic memory chip select 2 (up to 256 mb). 0xb800 0000 - 0xbfff ffff dynamic memory chip select 3 (up to 256 mb). 0xe000 0000 to 0xe00f ffff cortex-m4 private peripheral bus 0xe000 0000 - 0xe00f ffff cortex-m4 related functions, includes the nvic and system tick timer. table 7. memory usage and details ?continued address range general use address range details and description
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 60 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller the private peripheral bus includes cpu peripherals such as the nvic, systick, and the core control registers. fig 9. lpc540xx memory mapping aaa-029064 memory space (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) boot rom (reserved) active interrupt vectors (emc) private peripheral bus peripheral bit-band addressing asynchronous apb peripherals apb peripherals on apb bridge 1 apb peripherals on apb bridge 0 sram bit-band addressing sram2 (up to 32 kb) sram1 (up to 32 kb) sram0 (up to 64 kb) spifi flash interface memory mapped space sramx (192 kb) ahb peripheral ahb peripherals 0x4009 b000 0x4009 a000 0x4009 9000 0x4009 8000 0x4009 7000 0x4009 6000 0x4009 5000 0x4009 4000 0x4009 2000 0x4009 1000 0x4009 0000 0x4008 c000 0x4008 b000 0x4008 a000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 0x4009 c000 0x4009 d000 0x4009 e000 0x4009 f000 0x400a 1000 0x400a 2000 0x4010 bfff 0x400a 3000 0x400a 4000 0x400a 5000 0x4010 0000 0x4010 2000 0x4004 0000 see apb memory map figure 0x4002 0000 0x0000 0000 0x0000 00c0 0x0000 0000 0x0003 0000 0x0300 0000 0x0301 0000 0x1000 0000 0x1800 0000 0x2000 0000 0x2001 0000 0x2001 8000 0x2002 0000 0x2002 8000 0x2400 0000 0x4000 0000 0x4006 0000 0x4008 0000 0x4010 c000 0x4200 0000 0x4400 0000 0x8000 0000 0xe000 0000 0xe010 0000 0xffff ffff fs usb host registers sha registers usb sram (8 kb) (reserved) hs usb host registers (reserved) adc (reserved) flexcomm 8 flexcomm 7 flexcomm 6 flexcomm 5 (reserved) can 1 can 0 sdio flexcomm 9 crc engine (reserved) dmic interface high speed gpio (reserved) flexcomm 4 flexcomm 3 flexcomm 2 flexcomm 1 flexcomm 0 sc timer / pwm fs usb device registers lcd registers dma registers emc registers spifi registers ethernet hs usb device flexcomm 10 0x400a 0000 sram3 (up to 32 kb) 0x2200 0000
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 61 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.10 system control 7.10.1 clock sources the lpc540xx supports one external and two internal clock sources: ? free running oscillator (fro). ? watchdog oscillator (wdosc). ? crystal oscillator. 7.10.1.1 free running oscillator (fro) the fro 12 mhz oscillator provides the def ault clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. ? 12 mhz internal fro oscillato r, factory trimmed for accura cy, that can optionally be used as a system clock as well as other purposes. ? selectable 48 mhz or 96 mhz fro oscillator, factory trimmed for accuracy, that can optionally be used as a system clock as well as other purposes. 7.10.1.2 watchdog oscillator (wdosc) the watchdog oscillator is a low-power internal oscillator. the wdosc can be used to provide a clock to the wwdt and to the entire chip. the low-power watchdog oscillator provides a selectable frequency in the range of 6 khz to 1.5 mhz. the accuracy of this clock is limited to ? 40% over temper ature, voltage, and silicon processing variations. fig 10. lpc540xx apb memory map 21-14 13 11-9 8 7-0 0x4003 6000 0x4002 d000 0x4002 c000 0x4002 9000 0x4002 8000 0x4002 0000 (reserved) (reserved) (reserved) rit ctimer2 apb bridge 1 20-15 14 13 12 11-10 9 8 0x4001 f000 0x4000 e000 0x4000 d000 0x4000 c000 0x4000 a000 0x4000 9000 0x4000 8000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 (reserved) mrt (reserved) ctimer0 wdt micro-tick ctimer1 apb bridge 0 7-6 5 4 3 2 1 input muxes gint1 iocon pin interrupts (pint) (reserved) gint0 0 syscon 31-10 9 8 7-1 0 0x4005 ffff 0x4004 a000 0x4004 9000 0x4004 8000 0x4004 1000 0x4004 0000 (reserved) ctimer3 asynch. syscon (reserved) ctimer4 asynchronous apb bridge aaa-029065 otp controller (reserved) 0x4001 ffff 0x4001 5000 21 31-22 smart card 0 smart card 1 22 23 0x4001 6000 (reserved) 0x4003 7000 0x4003 8000 0x4003 ffff 25-24 rtc 0x4002 e000 12 26 rng 31-28 (reserved) 0x4003 a000 0x4003 b000 27 (reserved) 0x4003 c000
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 62 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.10.1.3 crystal oscillator the lpc540xx include four inde pendent oscillators. these ar e the main oscillator, the fro, the watchdog oscillator, and the rtc oscillator. following reset, the lpc540xx will operate from the internal fro until switched by software. this allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. see figure 11 and figure 12 for an overview of the lpc540xx clock generation. 7.10.2 system pll (pll0) the system pll accepts an input clock frequency in the range of 32.768 khz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). the pll can be enabled or disabled by software. 7.10.3 usb pll (pll1) the usb pll accepts an input clock frequency in the range of 1 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). the pll can be enabled or disabled by software. 7.10.4 audio pll (pll2) the audio pll accepts an input clock frequency in the range of 1 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). the pll can be enabled or disabled by software.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 63 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.10.5 clock generation fig 11. lpc540xx clock generation 000 001 010 pll_clk fro_hf main_clk usb_pll_clk 011 audio_pll_clk adc clock divider adcclkdiv cpu clock divider to cpu, ahb bus, sync apb ahbclkdiv adc clock select system pll system pll settings 000 001 010 pll_clk fro_hf usb_pll_clk 111 none usb0 clock divider usb0clkdiv 00 01 10 clk_in fro_12m (1) (1) wdt_clk 11 fro_hf 00 10 11 pll_clk 32k_clk mainclksela[1:0] (1) (1): synchronized multiplexer, see register descriptions for details. asyncapbclksela[1:0] mainclkselb[1:0] 000 001 clk_in fro_12m 011 32k_clk 111 none syspllclksel[2:0] 000 001 010 fro_hf_div fro_12 audio_pll_clk 011 mclk_in 111 none dmic clock divider dmicclkdiv dmicclksel[2:0] usb0 clock select mclk divider mclkdiv mclk clock select 000 001 audpllcksel[2:0] audio pll settings fro_12m clk_in crystal oscillator range select sysoscctrl[1:0] clk_in emc clock divider to emc (function clock) aaa-029067 00 01 fro_12m main_clk audio_pll_clk fc6_fclk to async apb 000 001 fro_hf_div audio_pll_clk audio pll usb pll usb pll settings fro_hf_div usb1 clock select 000 001 010 pll_clk main_clk usb_pll_clk 111 none usb1 clock divider to usb1 phy usb1clkdiv to adc to usb0 to dmic subsystem to mclk pin (output) 111 none 111 none usb1clksel[2:0] 111 none 10 11 xtalin xtalout main clock select a pll clock select pll_clk main clock select b emcclkdiv fro clock divider frohfclkdiv fro_hf clk_in usb_pll_clk audio clock select audio_pll_clk apb clock select b adcclksel[2:0] (fs usb) usb0clksel[2:0] dmic clock select 000 001 010 100 sdio clock divider sdioclkdiv sdio clock select 011 to sdio (function clock) 111 pll_clk main_clk usb_pll_clk fro_hf audio_pll_clk none sdioclksel[2:0] mclkclksel[1:0] main_clk wdt_in 100 101 01 none
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 64 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 12. lpc540xx clock generation (continued) 00 01 10 lcdclkin main_clk fro_hf 11 lcd clock divider to lcd (function clock) lcdclkdiv lcdclksel[1:0] frg clock divider frgctrl[15:0] aaa-029070 000 001 010 pll_clk main_clk fro_12m 011 fro_hf 111 none frg clock select frgclksel[2:0] 000 001 010 fro_hf_div fro_12m audio_pll_clk 011 mclk_in 100 frg_clk 111 none fclksel[0-9] fcn_fclk (function clock of flexcomm[0-9]) clkout divider clkout clkoutdiv 000 001 010 clk_in main_clk wdt_clk 011 fro_hf 100 pll_clk 101 usb_pll_clk 110 audio_pll_clk 111 32k_clk clkoutsel[2:0] 32k_clk to clk32k of all flexcomms (fc0-fc9) (1 per flexcomm) 000 001 010 pll_clk main_clk 011 fro_hf 111 audio_pll_clk sctimer/pwm clock divider to sctimer/pwm input clock 7 sctclkdiv sctclksel[2:0] none none (up to 11 flexcomm interfaces on these devices) sct clock select lcd clock select clkout select to mcan0 function clock can0clkdiv main_clk mcan0 clock divider to mcan1 function clock can1clkdiv main_clk mcan1 clock divider to smartcard0 function clock sc0clkdiv main_clk smartcard0 clock divider to smartcard1 function clock sc1clkdiv main_clk smartcard1 clock divider to arm trace function clock armtraceclkdiv main_clk arm trace clock divider 000 001 010 pll_clk main_clk usb_pll_clk 011 fro_hf 100 audio_pll_clk spifi clock divider to spifi (function clock) spifi clkdiv spifi clock select spificlksel[2:0] 111 none systick clock divider systic clock select systickclksel[2:0] main_clk systickclkdiv 000 001 010 wdt_clk 32k_clk 111 none to cortex-m4 system tick timer 000 001 010 pll_clk main_clk usb_pll_clk 011 fro_hf 100 audio_pll_clk 111 none fclksel10 fcn_fclk (function clock of flexcomm10) 011 fro_12
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 65 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.10.6 brownout detection the lpc540xx includes a monitor for the voltage level on the v dd pin. if this voltage falls below a fixed level, the bod sets a flag that can be polled or cause an interrupt. in addition, a separate threshold level can be selected to cause chip reset. 7.10.7 safety the lpc540xx includes a windowed watchdog timer (wwdt), which can be enabled by software after reset. once enabled, the wwdt remains locked and cannot be modified in any way until a reset occurs. 7.11 power control the lpc540xx support a variety of power contro l features. in active mode, when the chip is running, power and clo cks to selected peripherals can be adjusted for power consumption. in addition, there are three special modes of processor power reduction with different peripherals running: sleep mode, deep-sleep mode, and deep power-down mode that can be activated using the power api library from the sdk software package. 7.11.1 sleep mode in sleep mode, the system clock to the cpu is stopped and execution of instructions is suspended until either a reset or an interrupt occurs. peripheral functions, if selected to be clocked can continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, internal buses, and unused peripherals. the processor state and registers, peripheral registers, and internal sram values are maintained, and the logic levels of the pins remain static. 7.11.2 deep-sleep mode in deep-sleep mode, the system clock to the pr ocessor is disabled as in sleep mode. all analog blocks are powered down by default but can be selected to keep running through the power api if needed as wake-up sources. the main clock and all peripheral clocks are disabled. the fro is disabled. deep-sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. the processor state and registers, peripheral registers, and internal sram values are maintained, and the logic levels of the pins remain static. gpio pin interrupts, gp io group interrupts, and selected peripherals such as usb0, usb1, dmic, spi, i2c, usart, wwdt, rtc, micro-tick timer, and bod can be left running in deep sleep mode the fro, rtc oscillator, and the watchdog oscillator can be left running.in some cases, dma can operate in deep-sleep mode. 7.11.3 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the rtc power domain and the reset pin. the lpc540xx can wake up from deep power-down mode via the reset pin and the rtc alarm. the alarm1hz flag in rtc control register generates an rtc wake-up interrupt request, which can wake up the part. during deep power-down mode, the contents of the sram and registers are not retained. all functional pins are tri-stated in deep power-down mode.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 66 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ta b l e 8 shows the peripheral configuration in reduced power modes. table 8. peripheral configuration in reduced power modes peripheral reduced power mode sleep deep-sleep deep power-down fro software configured software configured off bod software configured software configured off pll software configured off off watchdog osc and wwdt software configured software configured off micro-tick timer software configured software configured off dma active configurable some for operations. off usart software configured off; but can cr eate a wake-up interrupt in synchronous slave mode or 32 khz clock mode off spi software configured off; but can create a wake-up interrupt in slave mode off i2c software configured off; but can create a wake-up interrupt in slave mode off usb0 software configured software configured off usb1 software configured software configured off ethernet software configured off off dmic software configured software configured off other digital peripherals software configured off off rtc oscillator software configured software configured software configured
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 67 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ta b l e 9 shows wake-up sources for reduced power modes. table 9. wake-up sources for reduced power modes power mode wake-up source conditions sleep any interrupt enable interrupt in nvic. hwwake certain flexcomm interfac e and dmic subsystem activity. deep-sleep pin interrupts enable pin interrupts in nvic and starter0 and/or starter1 registers. bod interrupt ? enable interrupt in nvic and starter0 registers. ? enable interrupt in bodctrl register. ? configure the bod to keep running in this mode with the power api. bod reset enable reset in bodctrl register. watchdog interrupt ? enable the watchdog oscillator in the pdruncfg0 register. ? enable the watchdog interrupt in nvic and starter0 registers. ? enable the watchdog in the wwdt mod register and feed. ? enable interrupt in wwdt mod register. ? configure the wdtosc to keep running in this mode with the power api. watchdog reset ? enable the watchdog oscillator in the pdruncfg0 register. ? enable the watchdog and watchdog reset in the wwdt mod register and feed. reset pin always available. rtc 1 hz alarm timer ? enable the rtc 1 hz oscillator in the rtcoscctrl register. ? enable the rtc bus clock in the ahbclkctrl0 register. ? start rtc alarm timer by writing a time-out value to the rtc count register. ? enable the rtcalarm interrupt in the starter0 register. rtc 1 khz timer time-out and alarm ? enable the rtc 1 hz oscillator and the rtc 1 khz oscillator in the rtc ctrl register. ? start rtc 1 khz timer by writing a va lue to the wake register of the rtc. ? enable the rtc wake-up interrupt in the starter0 register. micro-tick timer (intended for ultra-low power wake-up from deep-sleep mode ? enable the watchdog oscillator in the pdruncfg0 register. ? enable the micro-tick timer clock by writing to the ahbclkctrl1 register. ? start the micro-tick timer by writing utick ct rl register. ? enable the micro-tick timer interrupt in the starter0 register. i2c interrupt interrupt fr om i2c in slave mode. spi interrupt interrupt from spi in slave mode. usart interrupt interrupt from usart in slave or 32 khz mode. usb0 need clock interrupt interrupt from usb0 when activity is detected that requires a clock. usb1 need clock interrupt interrupt from usb1 when activity is detected that requires a clock. ethernet interrupt interrupt from ethernet. dma interrupt interrupt from dma. hwwake certain flexcomm interfac e and dmic subsystem activity.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 68 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.12 general purpose i/o (gpio) the lpc540xx provides six gpio ports with a total of up to 171 gpio pins. device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the current level of a port pin can be read back no matter what peripheral is selected for that pin. 7.12.1 features ? accelerated gpio functions: ? gpio registers are located on the ahb so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? all gpio pins can be selected to create an edge or level-sensitive gpio interrupt request. ? one gpio group interrupt can be triggered by a combination of any pin or pins. 7.13 pin interrupt/pattern engine the pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the nvic. the pattern match engine can be used in conjunction with software to create complex state machines based on pin inputs. any digital pin, independent of the function se lected through the switch matrix can be configured through the syscon bl ock as an input to the pin interrupt or pattern match engine. the registers that control the pin inte rrupt or pattern match engine are located on the i/o+ bus for fast single-cycle access. deep power-down rtc 1 hz alarm timer ? enable the rtc 1 hz oscillator in the rtc ctrl register. ? start rtc alarm timer by writing a time-out value to the rtc count register. rtc 1 khz timer time-out and alarm ? enable the rtc 1 hz oscillator and the rtc 1 khz oscillator in the rtcoscc- trl register. ? enable the rtc bus clock in the ahbclkctrl0 register. ? start rtc 1 khz timer by writing a va lue to the wake register of the rtc. reset pin always available. table 9. wake-up sources for reduced power modes power mode wake-up source conditions
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 69 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.13.1 features ? pin interrupts: ? up to eight pins can be selected from all gpio pins on ports 0 and 1 as edge-sensitive or level-sensitive interrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrup t on rising or falling edges or both. ? level-sensitive interrupt pins can be high-active or low-active. ? level-sensitive interrupt pins can be high-active or low-active. ? pin interrupts can wake up the device from sleep mode and deep-sleep mode. ? pattern match engine: ? up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each bit slice minterm (product term) comprising of the specified boolean expression can generate its own, dedicated interrupt request. ? any occurrence of a pattern match can al so be programmed to generate an rxev notification to the cpu. the rxev signal can be co nnected to a pin. ? pattern match can be used in conjunctio n with software to create complex state machines based on pin inputs. ? pattern match engine facilities wake-up only fr om active and sleep modes. 7.14 serial peripherals 7.14.1 full-speed usb host/device interface (usb0) the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot plugging and dynamic configuration of the devi ces. all transactions are initiated by the host controller. 7.14.1.1 usb0 device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interf ace engine, endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. features ? supports 10 physical (5 logical) endpoints including two control endpoints. ? single and double-buffering supported. ? each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. ? supports wake-up from reduced power mode on usb activity and remote wake-up. ? supports softconnect. ? link power management (lpm) supported.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 70 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.14.1.2 usb0 host controller the host controller enables fu ll- and low-speed data exchange with usb devices attached to the bus. it consists of register interface, serial interface engine and dma controller. the register interface complies with the open ho st controller interfac e (ohci) specification. features ? ohci compliant. ? two downstream ports. 7.14.2 high-speed usb host/device interface (usb1) the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot plugging and dynamic configuration of the devi ces. all transactions are initiated by the host controller. 7.14.2.1 usb1 device controller the device controller enables 480 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interf ace engine, endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. features ? fully compliant with usb 2.0 specification (high speed). ? supports 8 physical (16 logical) endpoints with up to 8 kb endpoint buffer ram. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? while usb is in the suspend mode, the lpc540xx can enter one of the reduced power modes and wake up on usb activity. ? double buffer implementation for bulk and isochronous endpoints. 7.14.2.2 usb1 host controller the host controller enables high speed data exchange with usb devices attached to the bus. it consists of register interface and se rial interface engine. the register interface complies with the enhanced host controller interface (ehci) specification. features ? ehci compliant. ? two downstream ports. ? supports per-port power switching.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 71 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.14.3 ethernet avb the ethernet block enables a host to transmit and receive data over ethernet in compliance with the ieee 802.3-2008 standard. the ethernet interface contains a full featured 10 mbps or 100 mbps ethernet mac (media access controller) designed to provide optimized performance through the use of dma hardware acceleration. 7.14.3.1 features ? 10/100 mbit/s ? dma support ? power management remote wake-up frame and magic packet detection ? supports both full-duplex and half-duplex operation ? supports csma/cd protocol for half-duplex operation. ? supports ieee 802.3x flow control for full-duplex operation. ? optional forwarding of received pause co ntrol frames to the user application in full-duplex operation. ? supports ieee 802.1as-2011 and 802.1-qav-2009 for audio video (av) traffic. ? software support for avb feature is ava ilable from nxp professional services. see nxp.com for more details. ? back-pressure support for half-duplex operation. ? automatic transmission of zero-quanta p ause frame on deassertion of flow control input in full-dup lex operation. ? supports ieee1588 time stamping and i eee 1588 advanced time stamping (ieee 1588-2008 v2). 7.14.4 spi flash interface (spifi) the spi flash interface allows low-cost seri al flash memories to be connected to the lpc540xx microcontroller with little performance penalty compared to parallel flash devices with higher pin count. after a few commands configure the interface at startup, the enti re flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or dma channels. simple sequences of commands handle erasure and programming. many serial flash devices use a half-duplex command-driven spi protocol for device setup and initialization and then move to a half -duplex, command-driven 4-bit protocol for normal operation. different serial flash vendo rs and devices accept or require different commands and command fo rmats. spifi provides sufficient flexibility to be compatible with common flash devices and includes extensio ns to help insure compatibility with future devices. 7.14.4.1 features ? interfaces to serial flash me mory in the main memory map. ? supports classic and 4-bit bidirectional serial protocols. ? half-duplex protocol compatible with various vendors and devices. ? quad spi flash interface with 1-, 2-, or 4- bit data at rates of up to 52 mb per second.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 72 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? supports dma access. ? provides xip (execute in place) feature to execute code directly from serial flash. 7.14.5 can flexible data (can fd) interface the lpc540xx contains two can fd interfaces, can fd 1 and can fd 2. 7.14.5.1 features ? conforms with can protocol version 2.0 part a, b and iso 11898-1. ? can fd with up to 64 data bytes supported. ? can error logging. ? autosar support. ? sae j1939 support. ? improved acceptance filtering. 7.14.6 dmic subsystem 7.14.6.1 features ? pulse-density modulation (pdm) data input for left and/or right channels on 1 or 2 buses. ? flexible decimation. ? 16 entry fifo for each channel. ? dc blocking or unaltered dc bias can be selected. ? data can be transferred using dma from deep-sleep mode without waking up the cpu, then automatically retu rning to deep-sleep mode. ? data can be streamed directly to i 2 s on flexcomm interface 7. 7.14.7 smart card interface 7.14.7.1 features ? two dma supported iso 7816 smart card interfaces. ? both asynchronous protocols, t = 0 and t = 1 are supported. 7.14.8 flexcomm interface serial communication 7.14.8.1 features ? usart with asynchronous operation or syn chronous master or slave operation. ? spi master or slave, with up to 4 slave selects. ? i 2 c, including separate master, slave, and monitor functions. ? two i2s functions using flexcomm interface 6 and flexcomm interface 7. ? data for usart, spi, and i2s traffic us es the flexcomm interface fifo. the i 2 c function does not use the fifo.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 73 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.14.8.2 spi serial i/o controller features ? maximum data rates of 48 mbit/s in master mode and 14 mbit/s in slave mode for spi functions. (flexcomm interface 0-9). ? maximum data rates of 50 mbit/s in master mode and 50 mbit/s in slave mode for spi functions (flexcomm interface10). ? data frames of 1 to 16 bits supported direct ly. larger frames supported by software or dma set-up. ? master and slave operation. ? data can be transmitted to a slave without the need to read incoming data. this can be useful while setting up an spi memory. ? control information can optionally be writ ten along with data. this allows very versatile operation, including ?any length? frames. ? four slave select input/outputs with selectable polarity and flexible usage. ? activity on the spi in slave mode allows wake-up from deep-sleep mode on any enabled interrupt. remark: texas instruments ssi and national microwire modes are not supported. 7.14.8.3 i 2 c-bus interface the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (f or example, an lcd driver) or a transmitter with the capability to both re ceive and send information (suc h as memory). transmitters and/or receivers can operate in either mast er or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. features ? all i2cs support standard, fast-mode, and fast-mode plus with data rates of up to 1mbit/s. ? all i2cs support high-speed slave mode with data rates of up to 3.4 mbit/s. ? independent master, slave, and monitor functions. ? supports both multi-master and multi-master with slave functions. ? multiple i 2 c slave addresses supported in hardware. ? one slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple i 2 c-bus addresses. ? 10-bit addressing supported with software assist. ? supports smbus. ? activity on the i2c in slave mode allows wake-up from deep-sleep mode on any enabled interrupt.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 74 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.14.8.4 usart features ? maximum bit rates of 6.25 mbit/s in asynchronous mode. ? the maximum supported bit rate for usart master synchronous mode is 24 mbit/s, and the maximum supported bit rate for usart slave synchronous mode is 12.5 mbit/s. ? 7, 8, or 9 data bits and 1 or 2 stop bits. ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? multiprocessor/multidrop (9-bit) mode with software address compare. ? rs-485 transceiver output enable. ? autobaud mode for automatic baud rate detection ? parity generation and checking: odd, even, or none. ? software selectable oversampling from 5 to 16 clocks in asynchronous mode. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator with auto-baud function. ? a fractional rate divider is shared among all usarts. ? interrupts available for receiver ready, tr ansmitter ready, receiver idle, change in receiver break detect, framing error, pari ty error, overrun, underrun, delta cts detect, and receiver sa mple noise detected. ? loopback mode for testing of data and flow control. ? in synchronous slave mode, wakes up the part from deep-sleep mode. ? special operating mode allows operation at up to 9600 baud using the 32.768 khz rtc oscillator as the uart clock. this mo de can be used while the device is in deep-sleep mode and can wake-up the device when a character is received. ? usart transmit and receive function s work with the syst em dma controller. 7.14.8.5 i 2 s-bus interface the i 2 s bus provides a standard communication interface for streaming data transfer applications such as digital audio or data collection. the i 2 s bus specification defines a 3-wire serial bus, having one data, one clock, and one word select/frame trigger signal, providing single or dual (mono or stereo) audio data transfer as well as other configurations. in the lpc540xx, the i 2 s function is included in flexcomm interface 6 and flexcomm interface 7. each of the flexcomm interface implements four i 2 s channel pairs. the i 2 s interface within one flexcomm interface provides at least one channel pair that can be configured as a master or a slave. other channel pairs, if present, always operate as slaves. all of the channel pairs within one flexcomm interface share one set of i 2 s
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 75 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller signals, and are configured together for eit her transmit or receive operation, using the same mode, same data configuration and fram e configuration. all such channel pairs can participate in a time division multiplexing (tdm) arrangement. for cases requiring an mclk input and/or output, this is handled outside of the i 2 s block in the system level clocking scheme. features ? a flexcomm interface may implement one or more i 2 s channel pairs, the first of which could be a master or a slave, and the rest of which would be slaves. all channel pairs are configured together for either transmit or receive and other shared attributes. the number of channel pairs is defined for each flexcomm interface, and may be from 0 to 4. ? configurable data size for all channels within one flexcomm interface, from 4 bits to 32 bits. each channel pair can also be configured independently to act as a single channel (mono as opposed to stereo operation). ? all channel pairs within one flexcomm inte rface share a single bit clock (sck) and word select/frame trigger (ws), and data line (sda). ? data for all i 2 s traffic within one flexcomm interf ace uses the flexcomm interface fifo. the fifo depth is 8 entries. ? left justified and right justified data modes. ? dma support using fi fo level triggering. ? tdm (time division multiplexing) with a seve ral stereo slots and/ or mono slots is supported. each channel pair can act as any data slot. multiple channel pairs can participate as different slots on one tdm data line. ? the bit clock and ws can be selectively inverted. ? sampling frequencies supported depends on the specific device configuration and applications constraints (for example, system clock freq uency and pll availability.) but generally supports standard audio data rates. remark: the flexcomm interface function clock frequency should not be above 48 mhz. 7.15 digital peripheral 7.15.1 lcd controller the lcd controller provides all of the necessary control signals to interface directly to various color and monochrome lcd panels. both stn (single and dual panel) and tft panels can be operated. the display resolution is selectable and can be up to 1024 ? 768 pixels. several color modes are provided, up to a 24-bit true-color non-palettized mode. an on-chip 512 byte color pale tte allows reducing bus utilizat ion (that is, me mory size of the displayed data) while st ill supporting many colors. the lcd interface includes its own dma controlle r to allow it to operate independently of the cpu and other system functions. a built-in fifo acts as a buffer for display data, providing flexibility for system timing. hardware cursor su pport can furthe r reduce the amount of cpu time required to operate the display. 7.15.1.1 features ? ahb master interface to access frame buffer.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 76 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? setup and control via a separate ahb slave interface. ? dual 16-deep programmable 64-bit wide fifos for buffering incoming display data. ? supports single and dual-panel monochrome super twisted nematic (stn) displays with 4-bit or 8-bit interfaces. ? supports single and dual-panel color stn displays. ? supports thin film transi stor (tft) color displays. ? programmable display resolution including, but not limited to: 320 ? 200, 320 ? 240, 640 ? 200, 640 ? 240, 640 ? 480, 800 ? 600, and 1024 ? 768. ? hardware cursor support for single-panel displays. ? 15 gray-level monochrome, 3375 color stn, and 32 k color palettized tft support. ? 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome stn. ? 1, 2, 4, or 8 bpp palettized color displays for color stn and tft. ? 16 bpp true-color non-palettized for color stn and tft. ? 24 bpp true-color non-palettized for color tft. ? programmable timing for different display panels. ? 256 entry, 16-bit palette ram, arranged as a 128 ? 32-bit ram. ? frame, line, and pixel clock signals. ? ac bias signal for stn, data enable signal for tft panels. ? supports little and big-endian, and windows ce data formats. ? lcd panel clock may be generated from the peripheral clock, or from a clock input pin. 7.15.2 sd/mmc card interface the sd/mmc card interface support s the following mo des to control: 7.15.2.1 features ? secure digital memory (sd version 1.1). ? secure digital i/o (sdio version 2.0). ? consumer electronics advanced transport architecture (ce-ata version 1.1). ? multimedia cards (mmc version 4.1). ? supports up to a maximum of 50 mhz of interface frequency. 7.15.3 external memory controller the lpc540xx emc is an arm primecell multiport memory co ntroller peripheral offering support for asynchronous static memory dev ices such as ram, rom, and flash. in addition, it can be used as an interfac e with off-chip memory-mapped devices and peripherals. the emc is an advanced microc ontroller bus architecture (amba) compliant peripheral. 7.15.3.1 features ? read and write buffers to reduce latency and to improve performance. ? low transaction latency.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 77 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? asynchronous static memory device suppor t including ram, rom, and flash, with or without asynchronous page mode. ? 8/16/32 data and 16/20/26 address lines wide static memory support. ? static memory features include: ? asynchronous page mode read. ? programmable wait states. ? bus turnaround delay. ? output enable and write enable delays. ? extended wait. ? dynamic memory interface support in cluding single data rate sdram. ? 16 bit and 32 bit wide chip select sdram memory support. ? emc bus width (bit) on lqfp100 and tfbga100 packages supports up to 8/16 data line wide static memory. ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically cont rol emc_cke and emc_clk outputs to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2048 (a0 to a10), 4096 (a0 to a11), and 8192 (a0 to a12) row address synchronous memory parts. that is typical 512 mb, 256 mb, and 128 mb parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-r efresh through a chip reset if desired. note: synchronous static memory devices (synchronous burst mode) are not supported.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 78 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.15.4 dma controller the dma controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional dma transfers for a single source and destination. 7.15.4.1 features ? one channel per on-chip peripher al direction: typically one for input and one for output for most peripherals. ? dma operations can optionally be triggered by on- or off-chip events. ? priority is user selectable for each channel. ? continuous priority arbitration. ? address cache. ? efficient use of data bus. ? supports single transfers up to 1,024 words. ? address increment options allow packing and/or unpacking data. 7.16 counter/timers 7.16.1 general-purpose 32-bit timers/external event counter the lpc540xx includes five general-purpose 32-bit timer/counters. the timer/counter is design ed to count cycles of th e system derived clock or an externally-supplied clock. it can optionally generate interrupts , generate timed dma requests, or perform other actions at spec ified timer values, based on four match registers. each timer/counter al so includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.16.1.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? up to four 32-bit captures can take a snaps hot of the timer value when an input signal transitions. a capture event may also option ally generate an interrupt. the number of capture inputs for each timer that are actually available on device pins may vary by device. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? shadow registers are added for glitch-free pwm output. ? for each timer, up to four external outputs corresponding to match registers with the following capabilities (the number of match outputs for each time r that are actually available on device pins may vary by device): ? set low on match. ? set high on match.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 79 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? toggle on match. ? do nothing on match. ? up to two match registers can be used to generate timed dma requests. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? up to four match registers can be configured for pwm operation, allowing up to three single edged controlled pwm outputs. (the number of match outputs for each timer that are actually available on device pins may vary by device.) 7.16.2 sctimer/pwm the sctimer/pwm allows a wide variety of timi ng, counting, output modulation, and input capture operations. the inputs and output s of the sctimer/pwm are shared with the capture and match inputs/outputs of the 32-bit general-purpose counter/timers. the sctimer/pwm can be configured as two 16-bit counters or a unified 32-bit counter. in the two-counter case, in addition to the counter value the following operational elements are independent for each half: ? state variable. ? limit, halt, stop, and start conditions. ? values of match/capture re gisters, plus reload or capture control values. in the two-counter case, the following operational elements are global to the sctimer/pwm, but the last three can us e match conditions from either counter: ? clock selection ? inputs ? events ? outputs ? interrupts 7.16.2.1 features ? two 16-bit counters or one 32-bit counter. ? counter(s) clocked by bu s clock or selected input. ? up counter(s) or up-down counter(s). ? state variable allows sequencin g across multiple counter cycles. ? event combines input or output condition and/or counter match in a specified state. ? events control outputs, interrupts, and the sctimer/pwm states. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? selected event(s) can limit, halt, start, or stop a counter. ? supports:
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 80 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? 8 inputs ? 10 outputs ? 16 match/capture registers ? 16 events ? 16 states ? pwm capabilities including dead ti me and emergency abort functions 7.16.3 windowed watchdog timer (wwdt) the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.16.3.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) uses the wdosc as the clock source. 7.16.4 real time clock (rtc) timer the rtc timer is a 32-bit timer which counts down from a preset va lue to zero. at zero, the preset value is reloaded and the counter continues. the rtc timer uses the 32.768 khz clock input to create a 1 hz or 1 khz clock. 7.16.5 multi-rate timer (mrt) the multi-rate timer (mrt) provides a repetiti ve interrupt timer with four channels. each channel can be programmed with an independent time interval, and each channel operates independently fr om the other channels. 7.16.5.1 features ? 24-bit interrupt timer. ? four channels independently counting down from individually set values. ? repeat and one-shot interrupt modes.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 81 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.16.6 repetitive interrupt timer (rit) the repetitive interrupt timer provides a free-r unning 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. any bits of the timer/compare can be masked such that they do not contribute to the match detection. the repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.16.6.1 features ? 48-bit counter running from the main cloc k. counter can be free-running or can be reset when an rit interrupt is generated. ? 48-bit compare value. ? 48-bit compare mask. an interrupt is generated when the counter value equals the compare value, after masking. this allows for co mbinations not poss ible with a simple compare. ? can be used for etm debug time stamping. 7.17 12-bit analog-to-dig ital converter (adc) the adc supports a resolution of 12-bit and fast conversion rates of up to 5 msamples/s. sequences of analog-to-digital conversions can be triggered by multiple sources. possible trigger sources are the sctimer/pwm, exte rnal pins, and the arm txev interrupt. the adc supports a variable clocking scheme with clocking synchronous to the system clock or independent, asynchronous clocking for high-speed conversions the adc includes a hardware threshold compar e function with zero-crossing detection. the threshold crossing interrupt is connect ed internally to the sctimer/pwm inputs for tight timing control between the adc and the sctimer/pwm. 7.17.1 features ? 12-bit successive approximation analog to digital converter. ? input multiplexing among up to 12 pins. ? two configurable conversion sequ ences with independent triggers. ? optional automatic high/low threshold comparison and ?zero crossing? detection. ? measurement range vrefn to vrefp (typically 3 v; not to exceed vdda voltage level). ? 12-bit conversion rate of 5.0 msamples/s. options for reduced resolution at higher conversion rates. ? burst conversion mode for single or multiple inputs. ? synchronous or asynchronous operati on. asynchronous operation maximizes flexibility in choosing the ad c clock frequency, synchron ous mode minimizes trigger latency and can eliminate uncertainty and jitter in response to a trigger.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 82 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.18 crc engine the cyclic redundancy check (crc) genera tor with programmable polynomial settings supports several crc standards commonl y used. to save system power and bus bandwidth, the crc engine supports dma transfers. 7.18.1 features ? supports three common polynomials crc-ccitt, crc-16, and crc-32. ? crc-ccitt: x 16 + x 12 + x 5 + 1 ? crc-16: x 16 + x 15 + x 2 + 1 ? crc-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? bit order reverse and 1?s complement programmable setting for input data and crc sum. ? programmable seed number setting. ? supports cpu pio or dma back-to-back transfer. ? accept any size of data width per write: 8, 16 or 32-bit. ? 8-bit write: 1-cycle operation. ? 16-bit write: 2-cycle op eration (8-bit x 2-cycle). ? 32-bit write: 4-cycle operation (8-bit x 4-cycle). 7.19 temperature sensor the temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a ctat voltage (complement to absolute temperature). the output voltage varies inversely with device temperature with an absolute accuracy of better than 5 ? c over the full temperature range ( ? 40 ? c to +105 ? c). the temperature sensor is only approximately linear with a slight curvature. the output voltage is measured over different ranges of temperatures and fi t with linear-least-square lines. after power-up, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate adc input. for an accurate measurement of the temper ature sensor by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result. 7.20 security features ? otp memories for aes key st orage and customer use. ? random number generator (rng). ? unique id for each device. 7.20.1 sha-1 and sha-2 the hash peripheral is used to perform sha-1 and sha-2 (256) based hashing. a hash takes an arbitrarily large message or imag e and forms a relatively small fixed size ?unique? number called a digest. the data is fed by words from the processor, dma, or hosted access; the words are converted from little-endian (arm standard) to big-endian (sha standard) by the block.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 83 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 7.20.1.1 features ? secure hash algorithm (sha1/sha2) module with dedicated dma controller. ? used with an hmac to support a challenge/response or to validate a message. ? can be used to verify external memory that has not been compromised. 7.21 emulation and debugging debug and trace functions are integrated into the arm cortex-m4. serial wire debug and trace functions are supported. the arm cortex-m4 is configured to support up to eight breakpoints and four watch points. the arm sysreq reset is suppor ted and causes the processor to rese t the peripherals, execute the boot code, restart from address 0x0000 0000, and break at the user entry point. the swd pins are multiplexed with other digital i/o pins. on reset, the pins assume the swd functions by default.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 84 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 8. limiting values table 10. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) on pin vdd [2] -0.5 +4.6 v v dda analog supply voltage on pin vdda -0.5 +4.6 v v bat battery supply voltage on pin vbat -0.5 +4.6 v v ref reference voltage on pin vrefp - -0.5 +4.6 v v i input voltage only valid when the v dd > 1.8 v; 5 v tolerant i/o pins [6][7] -0.5 +5.0 v on i2c open-drain pins [5] -0.5 +5.0 v usb_dm, usb_dp pins -0.5 +5.0 v v ia analog input voltage on digital pins configured for an analog function [8][9] -0.5 vdd v i dd supply current per supply pin, 1.71 v ? v dd < 2.7 v [3] -200ma supply current per supply pin, 2.7 v ? v dd < 3.6 v [3] -300ma i ss ground current per ground pin, 1.71 v ? v dd < 2.7 v [3] -200ma ground current per ground pin, 2.7 v ? v dd < 3.6 v [3] -300ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c -100ma t stg storage temperature [10] -65 +150 ? c t j(max) maximum junction temperature -+150 ? c
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 85 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. c) the limiting values are stress ratings only and operating the pa rt at these values is not recommended and proper operation is not guaranteed. the conditions for functi onal operation are specified in table 20 . [2] maximum/minimum voltage above the maximum operating voltage (see table 20 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] the peak current is limited to 25 times the corresponding maximum current. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. [5] v dd present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd is powered down. [6] applies to all 5 v tolerant i/o pins except true open-drain pins. [7] including the voltage on outputs in 3-state mode. [8] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. p tot(pack) total power dissipation (per package) lqfp208, based on package heat transfer, not device power consumption [11] -1.2w lqfp208, based on package heat transfer, not device power consumption [12] -0.95w lqfp100, based on package heat transfer, not device power consumption [11] -0.82w lqfp100, based on package heat transfer, not device power consumption [12] -0.60w tfbga180, based on package heat transfer, not device power consumption [11] -0.95w tfbga180, based on package heat transfer, not device power consumption [13] -1.2w tfbga100, based on package heat transfer, not device power consumption [11] -0.57w tfbga100, based on package heat transfer, not device power consumption [13] -0.65w v esd electrostatic discharge voltage human body model; all pins [4] - 2000 v table 10. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 86 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [9] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] dependent on package type. [11] jedec (4.5 in ? 4 in); still air. [12] single layer (4.5 in ? 3 in); still air. [13] 8-layer (4.5 in ? 3 in); still air.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 87 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. table 11. thermal resistance symbol parameter conditions max/min unit lqfp208 package r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 33 ?? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 41 ?? 15 % ? c/w r th(j-c) thermal resistance from junction to case 16 ?? 15 % ? c/w lqfp100 package r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 48 ?? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 65 ?? 15 % ? c/w r th(j-c) thermal resistance from junction to case 19 ?? 15 % ? c/w tfbga180 package r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 41 ?? 15 % ? c/w 8-layer (4.5 in ? 3 in); still air 33 ?? 15 % ? c/w r th(j-c) thermal resistance from junction to case 14 ?? 15 % ? c/w tfbga100 package r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 69 ?? 15 % ? c/w 8-layer (4.5 in ? 3 in); still air 60 ?? 15 % ? c/w r th(j-c) thermal resistance from junction to case 10 ?? 15 % ? c/w t j t amb p d r th j a ? ?? ? ?? + =
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 88 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 10. static characteristics 10.1 general operating conditions [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] attempting to program below 2.7 v will result in unpredict able results and the part might enter an unrecoverable state. 10.2 coremark data [1] clock source fro. pll disabled. [2] clock source 12 mhz fro. pll enabled. [3] characterized through bench m easurements using typical samples. [4] compiler settings: iar c/c++ compiler for arm ver 8.22.2, optimization level 3, optimized for time on. [5] sram1, sram2, sram3, and usb sram powered down. sram0 and sramx powered. table 12. general operating conditions t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit f clk cpu clock frequency - - 180 mhz cpu clock frequency for usb high-speed device and host operations 60 - 180 mhz cpu clock frequency for usb full-speed device and host operations 12 - 180 mhz v dd supply voltage (core and external rail) 1.71 - 3.6 v for otp programming only [2] 2.7 - 3.6 v for usb operation only 3.0 - 3.6 v v dda analog supply voltage 1.71 - 3.6 v v bat battery supply voltage 1.71 - 3.6 v v refp adc positive reference voltage v dda ?? 2 v 2.0 - v dda v v dda < 2 v v dda -v dda v rtc oscillator pins v i(rtcx) 32.768 khz oscillator input voltage on pin rtcxin -0.5 - +3.6 v v o(rtcx) 32.768 khz oscillator output voltage on pin rtcxout -0.5 - +3.6 v v i(xtal) crystal input voltage on pin xtalin ? 0.5 - 1.95 v v o(xtal) crystal output voltage on pin xtalout ? 0.5 - 1.95 v table 13. coremark score t amb =25 ? c, v dd = 3.3v parameter conditions typical unit arm cortex-m4 in active mode coremark score coremark code executed from sramx; cclk = 12 mhz [1][3][4][5] 3.38 (iterations/s) / mhz cclk = 96 mhz [1][3][4][5] 3.38 (iterations/s) / mhz cclk = 180 mhz [2][3][4][5] 3.38 (iterations/s) / mhz
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 89 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller conditions: v dd = 3.3 v; t amb = 25 c; active mode; all peri pherals disabled; bod disabled; measured with iar ver 8.22.2. optimization level 3, optimized for time on. 12 mhz, 24 mhz, 48 mhz, and 96 mhz: fro enabled; pll disabled. 36 mhz, 60 mhz, 72 mhz, 84 mhz, 108 mhz, 120 mhz, 132 mhz, 144 mhz, 156 mhz, 168 mhz, and 180 mhz: fro enabled; pll enabled. coremark score from sramx: sram0 is powered. fig 13. typical coremark score ((iteration s/s)/mhz) vs. frequency (mhz) from sramx ddd )uhtxhqf\0+] &ruhpdunvfruh & r u h p d u n v f r u h &ruhpdunvfruh lwhudwlrqvv0+] l w h u d w l r q v v 0 + ] lwhudwlrqvv0+] 065$0 0 6 5 $ 0 065$0
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 90 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 10.3 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions: ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 1 to the gpio clr register to drive the outputs low. ? all peripherals disabled. [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c), 3.3v. [2] clock source fro. pll disabled. [3] characterized through bench m easurements using typical samples. [4] compiler settings: keil uvision v.5.23, opt imization level 0, optimized for time off. [5] clock source fro. pll enabled. table 14. static characteristics: power consumption in active and sleep mode t amb = ? 40 ? c to +105 ? c, unless otherwise specified.1.71 v ? v dd ? 3.6 v. symbol parameter conditions min typ [1] max unit active mode i dd supply current coremark code executed from sramx: cclk = 12 mhz [2][3][4] -3.0-ma cclk = 96 mhz [2][3][4] -16.0-ma cclk = 180 mhz [3][4][5] -35.0-ma sleep mode i dd supply current cclk = 12 mhz [2][3][4] -1.7-ma cclk = 96 mhz [2][3][4] -4.1-ma cclk = 180 mhz [3][4][5] -8.3-ma
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 91 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c), vdd = 1.8 v. [2] characterized through bench m easurements using typical samples. [3] tested in production. vdd = 1.71 v. at hot temperature and below 2.0 v, the supply current increases slightly because of red uction of available rbb (reverse body bias) voltage. conditions: v dd = 3.3 v; t amb = 25 c; active mode; all peri pherals disabled; bod disabled; measured with keil uvision v.5.23. optimi zation level 0, optimized for time off. 12 mhz, 24 mhz, 48 mhz, and 96 mhz: fro enabled; pll disabled. 36 mhz, 60 mhz, 72 mhz, 84 mhz, 108 mhz, 120 mhz, 132 mhz, 144 mhz, 156 mhz, 168 mhz, and 180 mhz: fro enabled; pll enabled. coremark ? a/mhz from sramx: sram0 is powered. fig 14. coremark power consumption: typical ? a/mhz vs. frequency (mhz) sramx ddd )uhtxhqf\0+] ?$0+] ? $ 0 + ] ?$0+] 065$0)52 0 6 5 $ 0 ) 5 2 065$0)52 065$0)523// 0 6 5 $ 0 ) 5 2 3 / / 065$0)523// table 15. static characteristics: power consumpt ion in deep-sleep and deep power-down modes t amb = ? 40 ? c to +105 ? c, unless otherwise specified, 1.71 v ? v dd ? 2.2 v. symbol parameter conditions min typ [1][2] max [3] unit i dd supply current deep-sleep mode: sramx (64kb) powered t amb =25 ? c -54 175 ? a sramx (64 kb) powered t amb = 105 ? c - - 2092 ? a deep power-down mode rtc oscillator input grounded (rtc oscillator disabled) t amb =25 ? c - 709 1.1 ? a rtc oscillator input grounded (rtc oscillator disabled) t amb =105 ? c -- 27 ? a rtc oscillator running with external crystal vdd = vdda = vrefp = vbat = 1.8 v - 320 - na
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 92 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c), vdd = 3.3 v. [2] characterized through bench m easurements using typical samples. [3] tested in production, vdd = 3.6 v. [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c). [2] characterized through bench m easurements using typical samples. [3] if vbat> vdd, the external reset pin must be floating to prevent high vbat leakage. table 16. static characteristics: power consumpt ion in deep-sleep and deep power-down modes t amb = ? 40 ? c to +105 ? c, unless otherwise specified, 2.2 v ? v dd ? 3.6 v. symbol parameter conditions min typ [1][2] max [3] unit i dd supply current deep-sleep mode: sramx (64 kb) powered t amb =25 ? c -55 175 ? a sramx (64 kb) powered t amb = 105 ? c - - 2020 ? a deep power-down mode rtc oscillator input grounded (rtc oscillator disabled) t amb =25 ? c - 891 1.6 ? a rtc oscillator input grounded (rtc oscillator disabled) t amb =105 ? c -- 42 ? a rtc oscillator running with external crystal vdd = vdda= vrefp = 3.3 v, vbat = 3.0 v - 660 - na table 17. static characteristics: power consumption in deep power-down mode t amb = ? 40 ? c to +105 ? c, unless otherwise specified, 2.7 v ? v dd ? 3.6 v. symbol parameter conditions min typ [1][2] max unit i bat battery supply current deep power-down mode; rtc oscillator running with external crystal vdd = vdda= vrefp = 3.3 v, vbat = 3.0 v - 0 - na vdd = vdda= vrefp = 0 v or tied to ground, vbat = 3.0 v - 380 [3] -na
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 93 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ta b l e 1 8 shows the typical peripheral power consumption measured on a typical sample at tamb = 25 c and vdd = 3.3 v. the supply current per peripheral is measured as the difference in supply current between the perip heral block enabled and the peripheral block disabled using asyncapbclkctrl, ah bclkctrl0/1/2, and pdruncfg0/1 conditions: bod disabled; all os cillators and analog blocks disabl ed; all sram disabled except 64 kb sramx. remark: at hot temperature and below 2.0 v, the supp ly current increases slightly because of reduction of available rbb (reverse body bias) voltage. fig 15. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd rtc disabled (rtc oscillator input grounded). fig 16. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd ddd 7hpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9 ddd 7hpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 94 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller registers. all other blocks are disabled and no code accessing the peripheral is executed. the supply currents are show n for system clock frequencies of 12 mhz, 48 mhz, 96 mhz and 180mhz. [1] the supply current per peripheral is measured as t he difference in supply current between the peripheral block enabled and the peripheral block disabled using pdruncfg0/1 regi sters. all other blocks are disabled and no code accessing the peripheral is executed. [2] typical ratings are not guaranteed. characteriz ed through bench measurements using typical samples. table 18. typical peripheral power consumption [1][2] v dd = 3.3 v; t amb = 25 c peripheral i dd in ua fro 100 wdt osc 2.0 bod 2.0 table 19. typical ahb/apb peri pheral power consumption [3][4][5] t amb = 25 c, v dd = 3.3 v; peripheral i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz ahb peripheral cpu: 12 mhz, sync apb bus: 12 mhz cpu: 48 mhz, sync apb bus: 48 mhz cpu: 96 mhz, sync apb bus: 96 mhz cpu: 180 mhz, sync apb bus: 180 mhz usb0 device 0.3 0.3 0.3 0.4 usb1 device 4.4 4.4 4.4 5.0 dmic 0.2 0.2 0.2 0.2 gpio0 [1] 0.9 0.9 0.9 1.0 gpio1 [1] 0.8 0.8 0.8 1.0 gpio2 [1] 1.0 1.0 1.0 1.1 gpio3 [1] 1.1 1.1 1.1 1.3 gpio4 [1] 1.0 1.0 1.0 1.2 gpio5 [1] 0.7 0.7 0.7 0.8 dma 0.7 0.7 0.7 0.8 crc 1.0 1.0 1.0 1.0 adc0 1.6 1.6 1.6 1.9 sctimer/pwm 4.5 4.5 4.5 5.3 ethernet avb 24. 0 24.0 24.0 28.0 lcd 13.0 13.0 13.0 15.0 emc 39.0 39.0 39.0 45.4 can0 10.8 10.8 10.8 12.6 can1 10.7 10.7 10.7 12.4 sd/mmc 7.9 7.9 7.9 9.3 flexcomm interface 0 (usart, spi, i 2 c) 1.6 1.6 1.6 1.9 flexcomm interface1 (usart, spi, i 2 c) 1.6 1.6 1.6 1.8 flexcomm interface 2 (usart, spi, i 2 c) 1.7 1.7 1.7 1.9
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 95 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller flexcomm interface 3 (usart, spi, i 2 c) 1.4 1.4 1.4 1.6 flexcomm interface 4 (usart, spi, i 2 c) 1.4 1.5 1.5 1.7 flexcomm interface 5 (usart, spi, i 2 c) 1.7 1.7 1.7 1.9 flexcomm interface 6 (usart, spi, i 2 c, i 2 s) 2.0 2.0 2.0 2.3 flexcomm interface 7 (usart, spi, i 2 c, i 2 s) 1.6 1.6 1.6 1.9 flexcomm interface 8 (usart, spi, i 2 c) 1.5 1.5 1.5 1.8 flexcomm interface 9 (usart, spi, i 2 c) 1.5 1.5 1.5 1.8 flexcomm interface 10 (spi) 1.5 1.5 1.5 1.8 sync apb peripheral cpu: 12 mhz, sync apb bus: 12 mhz cpu: 48 mhz, sync apb bus: 48 mhz cpu: 96 mhz, sync apb bus: 96 mhz cpu: 180 mhz, sync apb bus: 180 mhz inputmux [1] 0.83 0.85 0.86 1.0 iocon [1] 2.67 2.65 2.65 3.13 pint 1.1 1.1 1.1 1.3 gint0 and gint1 1.33 1.35 1.34 1.52 wwdt 0.42 0.42 0.42 0.46 rtc 0.3 0.3 0.3 0.3 mrt 0.3 0.3 0.3 0.3 rit 0.1 0.1 0.1 0.1 utick 0.2 0.2 0.2 0.2 ctimer0 0.8 0.8 0.8 0.9 ctimer1 0.8 0.9 0.9 1.0 ctimer2 0.83 0.85 0.88 0.99 smart card0 2.5 2.5 2.5 2.8 smart card1 2.5 2.5 2.5 2.8 rng 1.4 1.4 1.4 1.5 otp controller 4.0 4.0 4.0 4.5 sha 1.2 1.2 1.2 1.3 table 19. typical ahb/apb peri pheral power consumption [3][4][5] t amb = 25 c, v dd = 3.3 v; peripheral i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 96 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] turn off the peripheral when the configuration is done. [2] for optimal system power consumption, use fix ed low frequency async apb bus when the cpu is at a higher frequency. [3] the supply current per peripheral is measured as t he difference in supply current between the peripheral block enabled and the peripheral block disabled using asyncapbc lkctrl, ahbclkctrl0/1, and pdruncfg0/1 registers. all other blocks are dis abled and no code accessing the peripheral is executed. [4] the supply currents are shown for system clock frequencies of 12 mhz, 48 mhz, 96 mhz and 180 mhz. [5] typical ratings are not guaranteed. characteriz ed through bench measurements using typical samples. 10.4 pin characteristics async apb peripheral cpu: 12 mhz, async apb bus: 12 mhz cpu: 48 mhz, sync apb bus: 12 mhz [2] cpu: 96 mhz, async apb bus: 12 mhz [2] cpu: 180 mhz, async apb bus: 12 mhz [2] timer3 0.9 0.9 0.9 0.9 timer4 0.9 0.9 0.9 0.9 table 19. typical ahb/apb peri pheral power consumption [3][4][5] t amb = 25 c, v dd = 3.3 v; peripheral i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz table 20. static characteri stics: pin characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.71 v ? v dd ? 3.6 v unless otherwise specif ied. values tested in production unless otherwise specified. symbol parameter conditions min typ [1] max unit reset pin v ih high-level input voltage 0.8 ? v dd -5.0v v il low-level input voltage ? 0.5 - 0.3 ? v dd v v hys hysteresis voltage [14] 0.05 ? v dd -- v standard i/o pins input characteristics i il low-level input current v i = 0 v; on-chip pull-up resistor disabled. -3.0180na i ih high-level input current v i =v dd ; v dd = 3.6 v; for resetn pin. 3.0 180 na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -3.0180na v i input voltage pin configured to provide a digital function; v dd ? 1.8 v [3] 0-5.0v v dd = 0 v 0 - 3.6 v v ih high-level input voltage 1.71 v ? v dd < 2.7 v 1.5 - 5.0 v 2.7 v ? v dd ? 3.6 v 2.0 - 5.0 v v il low-level input voltage 1.71 v ? v dd <2.7 v ? 0.5 - +0.4 v 2.7 v ? v dd ? 3.6 v ? 0.5 - +0.8 v v hys hysteresis voltage [14] 0.1 ? v dd -- v output characteristics v o output voltage output active 0 - v dd v
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 97 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller i oz off-state output current v o =0v; v o = v dd ; on-chip pull-up/pull-down resistors disabled -3180na v oh high-level output voltage i oh = ? 4 ma; 1.71 v ? v dd < 2.7 v v dd ? 0.4 - - v i oh = ? 6 ma; 2.7 v ? v dd ? 3.6 v v dd ? 0.4 v ol low-level output voltage i ol = 4 ma; 1.71 v ? v dd < 2.7 v - - 0.4 v i ol = 6 ma; 2.7 v ? v dd ? 3.6 v - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v; 1.71 v ? v dd <2.7 v 4.0 - - ma v oh =v dd ? 0.4 v; 2.7 v ? v dd ? 3.6 v 6.0 - - ma i ol low-level output current v ol = 0.4 v; 1.71 v ? v dd < 2.7 v 4.0 - - ma v ol = 0.4 v; 2.7 v ? v dd ? 3.6 v 6.0 - - ma i ohs high-level short-circuit output current 1.71 v ? v dd < 2.7 v [2][4] --35ma drive high; connected to ground; 2.7 v ? v dd ? 3.6 v - - 87 ma i ols low-level short-circuit output current 1.71 v ? v dd < 2.7 v [2][4] --30ma drive low; connected to v dd 2.7 v ? v dd ? 3.6 v - - 77 ma weak input pull-up/pull-down characteristics i pd pull-down current v i = v dd 25 80 ? a v i = 5 v [2] 80 100 ? a i pu pull-up current v i = 0 v ? 25 ? 80 ? a v dd < v i < 5 v [2][7] 630 ? a open-drain i 2 c pins v ih high-level input voltage 1.71 v ? v dd < 2.7 v 0.7 ? v dd -- v 2.7 v ? v dd ? 3.6 v 0.7 ? v dd -- v v il low-level input voltage 1.71 v ? v dd < 2.7 v 0 - 0.3 ? v dd v 2.7 v ? v dd ? 3.6 v 0 - 0.3 ? v dd v v hys hysteresis voltage 0.1 ? v dd -- v i li input leakage current v i =v dd [5] -2.53.5 ? a v i =5v - 5.5 10 ? a i ol low-level output current v ol = 0.4 v; pin configured for standard mode or fast mode 4.0 - - ma v ol = 0.4v; pin configured for fast-mode plus 20 - - ma table 20. static characteri stics: pin characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.71 v ? v dd ? 3.6 v unless otherwise specif ied. values tested in production unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 98 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltage. [2] based on characterization. not tested in production. [3] with respect to ground. [4] allowed as long as the current limit does not exceed the maximum current allowed by the device. [5] to v ss . [6] the values specified are simulated and absol ute values, including package/bondwire capacitance. [7] the weak pull-up resistor is connected to the v dd rail and pulls up the i/o pin to the v dd level. [8] the value specified is a simulated va lue, excluding package/ bondwire capacitance. [9] without 33 ? ? 2 % series external resistor. [10] the parameter values specified are simulated and absolute values. [11] with 33 ? ? 2 % series external resistor. [12] with 15 k ? ? 5 % resistor to v ss . [13] with 1.5 k ? ? 5% resistor to 3.6 v external pull-up. [14] guaranteed by design, not tested in production. usb0_dm and usb0_dp pins v i input voltage 0 - v dd v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v z out output impedance [11] 33.0 - 44 ? v oh high-level output voltage [12] 2.8 - - v v ol low-level output voltage [13] --0.3v i oh high-level output current v oh =v dd ? 0.3 v [9][10] 38 - 74 ma v oh =v dd ? 0.3 v [10][11] 6.0 9.0 ma i ol low-level output current v ol = 0.3 v [9][10] 38 - 74 ma v ol = 0.3 v [10][11] 6.0 9.0 ma i ols low-level short-circuit output current drive low; pad connected to ground [10] --100ma i ohs high-level short-circuit output current drive high; pad connected to ground [10] --100ma pin capacitance c io input/output capacitance i 2 c-bus pins [8] --6.0pf pins with digital functions only [6] --2.0pf pins with digital and analog functions [6] --7.0pf table 20. static characteri stics: pin characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.71 v ? v dd ? 3.6 v unless otherwise specif ied. values tested in production unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 99 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 10.4.1 electrical pin characteristics fig 17. pin input/output current measurement aaa-010819 + - pin pio0_n i oh ipu - + pin pio0_n i ol i pd v dd a a conditions: v dd = 1.8 v; on pins pio0_13 to pio0_14. conditions: v dd = 3.3 v; on pins pio0_13 to pio0_16. fig 18. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & &
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 100 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller conditions: v dd = 1.8 v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 19. typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & conditions: v dd = 1.8 v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 20. typical high-level output voltage v oh versus high-level output source current i oh ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & & ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & &
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 101 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller conditions: v dd = 1.8 v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 21. typical pull-up current i pu versus input voltage v i ddd 9 , 9 , sx s x , sx ?$ ? $ ?$ & & & & & & & & & & & & ddd 9 , 9 , sx s x , sx ?$ ? $ ?$ & & & & & & & & & & & & conditions: v dd = 1.8v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 22. typical pull-down current i pd versus input voltage v i ddd 9 , 9 , sg s g , sg ?$ ? $ ?$ & & & & & & & & & & & & ddd 9 , 9 , sg s g , sg ?$ ? $ ?$ & & & & & & & & & & & &
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 102 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11. dynamic characteristics 11.1 i/o pins [1] simulated data, not tested in production. [2] simulated using 10 cm of 50 ? pcb trace with 5 pf receiver input. rise and fall times measured between 80 % and 20 % of the full output signal level. [3] the slew rate is configured in the iocon block the slew bit. [4] c l = 20 pf. rise and fall times measured between 90 % and 10 % of the full input signal level. table 21. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +105 ? c; 1.71 v ? v dd ? 3.6 v symbol parameter conditions min typ max unit standard i/o pins - normal drive strength t r rise time pin configured as output; slew = 1 (fast-mode); 2.7 v ? v dd <= 3.6 v [2][3] 1.0 - 2.5 ns 1.71 v ? v dd <= 1.98 v 1.6 - 3.8 ns t f fall time pin configured as output; slew = 1 (fast-mode); 2.7 v ? v dd <= 3.6 v [2][3] 0.9 - 2.5 ns 1.71 v ? v dd <= 1.98 v 1.7 - 4.1 ns t r rise time pin configured as output; slew = 0 (standard mode); 2.7 v ? v dd ?? 3.6 v [2][3] 1.9 - 4.3 ns 1.71 v ? v dd ? 1.98 v 2.9 - 7.8 ns t f fall time pin configured as output; slew = 0 (standard mode); 2.7 v ? v dd ? 3.6 v [2][3] 1.9 - 4.0 ns 1.71 v ? v dd ? 1.98 v 2.7 - 6.7 ns t r rise time pin configured as input [4] 0.3 - 1.3 ns t f fall time pin configured as input [4] 0.2 - 1.2 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 103 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.2 wake-up process [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the wake-up time measured is the time between when a gpio input pin is trigger ed to wake the device up from the low power modes and from when a gpio output pin is set in the interrupt service routine (isr) wake-up handler. [3] fro enabled, all peripherals off. pll disabled. [4] rtc disabled. wake up from deep power-down causes the part to go through entire reset process. the wake-up time measured is the time between when the reset pin is triggered to wake the device up and when a gpio output pin is set in the reset handler. [5] fro disabled. table 22. dynamic characteristic: typica l wake-up times from low power modes v dd = 3.3 v;t amb =25 ? c; using fro as the system clock. symbol parameter conditions min typ [1] max unit t wake wake-up time from sleep mode [2][3] -2.0 - ? s from deep-sleep mode; sramx powered. sram0, sram1, sram2, sram3, and usb sram powered down. [2][5] -150 - ? s from deep power-down mode; rtc disabled; using reset pin. [4][5] -1.2 -ms
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 104 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.3 external memory interface table 23. dynamic characteristics: static external memory interface c l = 10 pf balanced loading on all pins, t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. max emc clock = 100 mhz. input slew = 1 ns; slew set to fast-mode. parameters sampled at th e 90 % and 10 % level of the rising or falling edge. excluding delays introduced by external device and pcb; values based on simulation. symbol parameter [1] conditions [1] min typ max unit read cycle parameters t cslav cs low to address valid time rd 1 ? 1.2 - 1.6 ns t csloel cs low to oe low time rd 2 [2] 0.4+ t cy(clk) ? waitoen -0.8+ t cy(clk) ? waitoen ns t cslblsl cs low to bls low time rd 3 ; pb = 1 [2][6] ? 1.6 - 0 ns t oeloeh oe low to oe high time rd 4 [2] (waitrd ? waitoen + 1) ? t cy(clk) -0.3 + (waitrd ? waitoen + 1) ? t cy(clk) ns t am memory access time rd 5 [2][3] ? 6.7 + (waitrd ? waitoen +1) ? t cy(clk) --ns t h(d) data input hold time rd 6 [2][4] ? 4.8 - - ns t cshblsh cs high to bls high time pb = 1 [6] 0.8 - 1.5 ns t cshoeh cs high to oe high time [2] 0.5 - 0.9 ns t oehanv oe high to address invalid time [2] ? 0.4 - 0 ns t deact deactivation time rd 7 [2] 0.5 - 0.9 ns write cycle parameters t cslav cs low to address valid time wr 1 0.1 - 0.5 ns t csldv cs low to data valid time wr 2 1.0 - 2.2 ns t cslwel cs low to we low time wr 3 ; pb =1 [2][6] ? 0.6 - 0 ns t cslblsl cs low to bls low time wr 4 ; pb = 1 [2][6] ? 1.2 - 0 ns t welweh we low to we high time wr 5 ; pb =1 [2][6] (waitwr ? waitwen + 1) ? t cy(clk) -0.1 + (waitwr ? waitwen + 1) ? t cy(clk) ns t blslblsh bls low to bls high time pb = 1 [2][6] 2.5 - 5.5 ns t wehdnv we high to data invalid time wr 6 ; pb =1 [2][6] 1.6 - 2.9 ns t weheow we high to end of write time wr 7 ; pb = 1 [2][5][6] 0.6 - 0.9 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 105 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] parameters are shown as rd n or wd n in figure 23 as indicated in the conditions column. [2] t cy(clk) = 1/emc_clk (see um11060 lpc540xx manual ). [3] latest of address valid, emc_csx low, emc_oe low, emc_blsx low (pb = 1). [4] after end of read (eor): earliest of emc_csx high, emc_oe high, emc_blsx high (pb = 1), address invalid. [5] end of write (eow): earliest of address invalid, emc_csx high, emc_blsx high (pb = 1). [6] the byte lane state bit, pb, enables diff erent types of memory to be connected (see the staticconfig[0:3] register in the um11060 lpc540xx manual ). t blshdnv bls high to data invalid time pb = 1 [6] ? 0.8 - 0 ns t wehanv we high to address invalid time pb = 1 [6] 0.6 - 0.9 ns t deact deactivation time wr 8 ; pb = 0; pb = 1 [2][6] ? 0.8 - 0 ns t cslblsl cs low to bls low wr 9 ; pb = 0 [2][6] ? 1.2 + (waitwen + 1) ? t cy(clk) - (waitwen + 1) ? t cy(clk) ns t blslblsh bls low to bls high time wr 10 ; pb = 0 [2][6] 2.5 + (waitwr ? waitwen + 1) ? t cy(clk) -5.5 + (waitwr ? waitwen + 1) ? t cy(clk) ns t blsheow bls high to end of write time wr 11 ; pb = 0 [2][5][6] ? 0.8 + t cy(clk) -t cy(clk) ns t blshdnv bls high to data invalid time wr12; pb = 0 [2][6] 0.2 + t cy(clk) - 0.5 + t cy(clk) ns table 23. dynamic characteristics: static external memory interface ?continued c l = 10 pf balanced loading on all pins, t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. max emc clock = 100 mhz. input slew = 1 ns; slew set to fast-mode. parameters sampled at th e 90 % and 10 % level of the rising or falling edge. excluding delays introduced by external device and pcb; values based on simulation. symbol parameter [1] conditions [1] min typ max unit table 24. dynamic characteristics: static external memory interface c l = 20 pf balanced loading on all pins, t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. max emc clock = 100 mhz. input slew = 1 ns; slew set to fast-mode. parameters sampled at th e 90 % and 10 % level of the rising or falling edge. excluding delays introduced by external device and pcb; values based on simulation. symbol parameter [1] conditions [1] min typ max unit read cycle parameters t cslav cs low to address valid time rd 1 ? 1.2 - 1.6 ns t csloel cs low to oe low time rd 2 [2] 0.5+ t cy(clk) ? waitoen -0.8+ t cy(clk) ? waitoen ns t cslblsl cs low to bls low time rd 3 ; pb = 1 [2][6] ? 2.3 - 0 ns t oeloeh oe low to oe high time rd 4 [2] (waitrd ? waitoen + 1) ? t cy(clk) -0.3 + (waitrd ? waitoen + 1) ? t cy(clk) ns t am memory access time rd 5 [2][3] ? 7.9 + (waitrd ? waitoen +1) ? t cy(clk) -- ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 106 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] parameters are shown as rd n or wd n in figure 23 as indicated in the conditions column. t h(d) data input hold time rd 6 [2][4] ? 5.5 - - ns t cshblsh cs high to bls high time pb = 1 [6] 0.7 - 1.5 ns t cshoeh cs high to oe high time [2] 0.5 - 0.9 ns t oehanv oe high to address invalid time rd 8 [2] ? 0.4 - 0 ns t deact deactivation time rd 7 [2] 0.5 - 0.9 ns write cycle parameters [2] t cslav cs low to address valid time wr 1 0.1 - 0.5 ns t csldv cs low to data valid time wr 2 1-2.2 ns t cslwel cs low to we low time wr 3 ; pb =1 [2][6] ? 0.5 + (waitwen + 1) ? t cy(clk) - (waitwen + 1) ? t cy(clk) ns t cslblsl cs low to bls low time wr 4 ; pb = 1 [2][6] ? 1.9 - 0 ns t welweh we low to we high time wr 5 ; pb =1 [2][6] ? 0.1 + (waitwen + 1) ? t cy(clk) - (waitwen + 1) ? t cy(clk) ns t blslblsh bls low to bls high time pb = 1 [2][6] 3.1 - 6.7 ns t wehdnv we high to data invalid time wr 6 ; pb =1 [2][6] 1.6 + t cy(clk) - 2.8 + t cy(clk) ns t weheow we high to end of write time wr 7 ; pb = 1 [2][5][6] 0.5 ? +t cy(clk) - 0.8 + t cy(clk) ns t blshdnv bls high to data invalid time pb = 1 [6] ? 0.8 - 0 ns t wehanv we high to address invalid time pb = 1 [6] 0.5 - 0.8 ns t deact deactivation time wr 8 ; pb = 0; pb = 1 [2][6] ? 0.8 - 0 ns t cslblsl cs low to bls low wr 9 ; pb = 0 [2][6] ? 1.9 + (waitwen + 1) ? t cy(clk) - (waitwen + 1) ? t cy(clk) ns t blslblsh bls low to bls high time wr 10 ; pb = 0 [2][6] 3.1+ (waitwr ? waitwen + 1) ? t cy(clk) -6.7+ (waitwr ? waitwen + 1) ? t cy(clk) ns t blsheow bls high to end of write time wr 11 ; pb = 0 [2][5][6] ? 0.8 + t cy(clk) -t cy(clk) ns t blshdnv bls high to data invalid time wr12; pb = 0 [2][6] 0.2 + t cy(clk) - 0.5 + t cy(clk) ns table 24. dynamic characteristics: static external memory interface ?continued c l = 20 pf balanced loading on all pins, t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. max emc clock = 100 mhz. input slew = 1 ns; slew set to fast-mode. parameters sampled at th e 90 % and 10 % level of the rising or falling edge. excluding delays introduced by external device and pcb; values based on simulation. symbol parameter [1] conditions [1] min typ max unit
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 107 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [2] t cy(clk) = 1/emc_clk (see um11060 lpc540xx manual ). [3] latest of address valid, emc_csx low, emc_oe low, emc_blsx low (pb = 1). [4] after end of read (eor): earliest of emc_csx high, emc_oe high, emc_blsx high (pb = 1), address invalid. [5] end of write (eow): earliest of address invalid, emc_csx high, emc_blsx high (pb = 1). [6] the byte lane state bit, pb, enables diff erent types of memory to be connected (see the staticconfig[0:3] register in the um11060 lpc540xx manual ). fig 23. external static memory read/write access (pb = 0) rd 1 rd 5 rd 2 wr 2 wr 9 wr 12 wr 10 wr 11 rd 5b rd 5a rd 6 wr 8 wr 1 eor eow rd 7 rd 4 emc_ax emc_csx emc_oe emc_blsx emc_we emc_dx aaa-026103 rd 8
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 108 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 24. external static memory read/write access (pb =1) rd 1 wr 1 emc_ax wr 8 wr 4 wr 8 emc_csx rd 2 rd 7 rd 7 rd 4 emc_oe emc_blsx emc_we rd 5 wr 6 wr 2 rd 5b rd 5c rd 5a rd 6 rd 3 eor eow emc_dx wr 3 wr 5 wr 7 aaa026104 rd 8 fig 25. external static memory burst read cycle rd 5 rd 5 rd 5 rd 5 emc_ax emc_csx emc_oe emc_blsx emc_we emc_dx 002aag216
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 109 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] refers to sdram clock signal emc_clkoutn where n = 0 and 1. [2] see table 27 for internal programmable delay. table 25. dynamic characteristics: dynamic external me mory interface, read strategy bits (rd bits) = 01 [2] c l = 10 pf balanced loading on all pins, t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. max emc clock = 100 mhz. input slew = 1 ns; slew set to fast-mode. parameters sampled at th e 90 % and 10 % level of the rising or falling edge. excluding delays introduced by external device and pcb. values based on simulation. t cmddly is programmable delay value for emc command outputs in command delayed mode; t fbdly is programmable delay value for the feedback clock that controls input data sampling. symbol parameter min typ max unit for rd = 1 common to read and write cycles t cy(clk) clock cycle time [1] 10 - - ns t d(sv) chip select valid delay time - - t cmddly + 3.7 ns t h(s) chip select hold time t cmddly + 1.7 - - ns t d(rasv) row address strobe valid delay time --t cmddly + 4.1 ns t h(ras) row address strobe hold time t cmddly + 1.8 - - ns t d(casv) column address strobe valid delay time --t cmddly + 4.4 ns t h(cas) column address strobe hold time t cmddly + 1.9 - - ns t d(wv) write valid delay time - - t cmddly + 5.1 ns t h(w) write hold time t cmddly + 2.4 - - ns t d(av) address valid delay time - - t cmddly + 4.8 ns t h(a) address hold time t cmddly + 1.7 - - ns read cycle parameters t su(d) data input set-up time 0.5 - - ns t h(d) data input hold time 2.1 - - ns write cycle parameters t d(qv) data output valid delay time - - 8.1 ns t h(q) data output hold time ? 1.7 - - ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 110 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] refers to sdram clock signal emc_clkoutn where n = 0 and 1. [2] see table 27 for internal programmable delay. table 26. dynamic characteristics: dynamic external me mory interface, read strategy bits (rd bits) = 01 [2] c l = 20 pf balanced loading on all pins, t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. max emc clock = 100 mhz. input slew = 1 ns; slew set to fast-mode. parameters sampled at th e 90 % and 10 % level of the rising or falling edge. excluding delays introduced by external device and pcb. values based on simulation. t cmddly is programmable delay value for emc command outputs in command delayed mode; t fbdly is programmable delay value for the feedback clock that controls input data sampling. symbol parameter min typ max unit for rd = 1 common to read and write cycles t cy(clk) clock cycle time [1] 10 - - ns t d(sv) chip select valid delay time - - t cmddly + 4.9 ns t h(s) chip select hold time t cmddly + 2.4 - - ns t d(rasv) row address strobe valid delay time --t cmddly + 5.4 ns t h(ras) row address strobe hold time t cmddly + 2.5 - - ns t d(casv) column address strobe valid delay time --t cmddly + 5.6 ns t h(cas) column address strobe hold time t cmddly + 2.6 - - ns t d(wv) write valid delay time - - t cmddly + 6.3 ns t h(w) write hold time t cmddly + 3.1 - - ns t d(av) address valid delay time - - t cmddly + 6.1 ns t h(a) address hold time t cmddly + 2.4 - - ns read cycle parameters t su(d) data input set-up time 0.5 - - ns t h(d) data input hold time 2.1 - - ns write cycle parameters t d(qv) data output valid delay time - - 9.3 ns t h(q) data output hold time ? 2.4 - - ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 111 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 26. dynamic external memory interface signal timing aaa-024988 t cy(clk) t h(q) t h(d) t su(d) emc_d[31:0] write emc_d[31:0] read t d(qv) t h(x) t d(xv) emc_clkout0 emc_clkout1 emc_dqmoutn emc_ckeoutn, emc_we, emc_ras, emc_dycsn, emc_cas, emc_a[22:0],
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 112 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] the programmable delay blocks are controlled by the emcdlyctl register in the emc register block. all delay times are incremental delays for eac h element starting from delay block 0. table 27. dynamic characteristics: dynamic external memory interface programmable clock delays (cmddly, fbclkdly) t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v.values guaranteed by design. t cmddly is programmable delay value for emc command outputs in command delayed mode; t fbdly is programmable delay value for the feedback clock that controls input data sampling. symbols parameter five bit value for each delay in emcdlyctl [1] min typ max unit t cmddly , t fbdly delay time b00000 0.41 0.66 0.77 ns b00001 0.52 0.85 1.03 ns b00010 0.69 1.11 1.3 ns b00011 0.8 1.3 1.56 ns b00100 0.95 1.53 1.77 ns b00101 1.06 1.72 2.03 ns b00110 1.23 1.98 2.3 ns b00111 1.34 2.17 2.56 ns b01000 1.45 2.3 2.67 ns b01001 1.56 2.49 2.93 ns b01010 1.73 2.75 3.2 ns b01011 1.84 2.94 3.46 ns b01100 1.99 3.17 3.67 ns b01101 2.1 3.36 3.93 ns b01110 2.27 3.62 4.2 ns b01111 2.38 3.81 4.46 ns b10000 2.45 3.86 4.46 ns b10001 2.56 4.05 4.72 ns b10010 2.73 4.31 4.99 ns b10011 2.84 4.5 5.25 ns b10100 2.99 4.73 5.46 ns b10101 3.1 4.92 5.72 ns b10110 3.27 5.18 5.99 ns b10111 3.38 5.37 6.25 ns b11000 3.49 5.5 6.36 ns b11001 3.6 5.69 6.62 ns b11010 3.77 5.95 6.89 ns b11011 3.88 6.14 7.15 ns b11100 4.03 6.37 7.36 ns b11101 4.14 6.56 7.62 ns b11110 4.31 6.82 7.89 ns b11111 4.42 7.01 8.15 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 113 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.4 system pll (pll0) [1] data based on characterization results, not tested in production. [2] pll current measured using lowest cco fr equency to obtain the desired output frequency. [1] data based on characterization results, not tested in production. [2] excluding under- and overshoot which ma y occur when the pll is not in lock. [3] a phase difference between the inputs of the pfd (c lkref and clkfb) smaller than the pfd lock criterion means lock output is high. [4] actual jitter dependent on amplitude and spectrum of substrate noise. [5] input clock coming from a crys tal oscillator with less than 250 ps peak-to-peak period jitter. table 28. pll lock times and current t amb = ? 40 ? c to +105 ? c, unless otherwise specified. v dd = 1.71 v to 3.6 v symbol parameter conditions min typ max unit pll0 configuration: input frequency 12 mhz; output frequency 100 mhz t lock(pll0) pll0 lock time [1] 96 ? s i dd(pll0) pll0 current when locked [1][2] --2.0ma pll0 configuration: input frequency 32 khz; output frequency 100 mhz t lock(pll0) pll0 lock time [1] - - 108 ? s i dd(pll0) pll0 current when locked [1][2] --1.6ma table 29. dynamic characteristics of the pll0 [1] symbol parameter conditions min typ max unit reference clock input f in input frequency 32.768 khz - 25 mhz clock output f o output frequency for pll0 clkout output [2] 4.3 - 550 mhz d o output duty cycle for pll0 clkout output 46 - 54 % f cco cco frequency 275 - 550 mhz lock detector output ? lock(pfd) pfd lock criterion [3] 124 ns dynamic parameters at f out = f cco = 540 mhz; standard bandwidth settings j rms-interval rms interval jitter f ref = 10 mhz [4][5] -1530 ps j pp-period peak-to-peak, period jitter f ref = 10 mhz [4][5] -4080 ps
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 114 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.5 usb pll (pll1) [1] data based on characterization results, not tested in production. [2] pll current measured using lowest cco fr equency to obtain the desired output frequency. [1] data based on simulation, not tested in production. [2] excluding under- and overshoot which ma y occur when the pll is not in lock. [3] actual jitter dependent on amplitude and spectrum of substrate noise. [4] input clock coming from a crys tal oscillator with less than 250 ps peak-to-peak period jitter. 11.6 audio pll (pll2) [1] data based on characterization results, not tested in production. [2] pll current measured using lowest cco fr equency to obtain the desired output frequency. table 30. pll1 lock times and current t amb = ? 40 ? c to +105 ? c, unless otherwise specified. v dd = 1.71 v to 3.6 v symbol parameter conditions min typ max unit pll1 configuration: input frequency 12 mhz; output frequency 48 mhz t lock(pll1) pll1 lock time [1] -7.4- ? s i dd(pll1) pll1 current when locked [1][2] - 260 - ? a table 31. dynamic charac teristics of the pll1 [1] symbol parameter conditions min typ max unit reference clock input f in input frequency 1 - 25 mhz clock output f o output frequency for pll1 clkout output [2] 9.75 - 160 mhz d o output duty cycle for pll1 clkout output 45 - 55 % f cco cco frequency 156 - 320 mhz dynamic parameters at f out = f cco = 320 mhz; standard bandwidth settings j pp-period peak-to-peak, period jitter f ref = 4 mhz [3][4] - - 300 ps table 32. pll2 lock times and current t amb = ? 40 ? c to +105 ? c, unless otherwise specified. v dd = 1.71 v to 3.6 v symbol parameter conditions min typ max unit pll2 configuration: input frequency 12 mhz; output frequency 100 mhz t lock(pll2) pll2 lock time [1] --96 ? s i dd(pll2) pll2 current when locked [1][2] --2.0ma pll2 configuration: input frequency 12 mhz; output frequency 100 mhz t lock(pll2) pll2 lock time [1] - - 108 ? s i dd(pll2) pll2 current when locked [1][2] --1.6ma
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 115 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] data based on characterization results, not tested in production. [2] excluding under- and overshoot which ma y occur when the pll is not in lock. [3] a phase difference between the inputs of the pfd (c lkref and clkfb) smaller than the pfd lock criterion means lock output is high. [4] actual jitter dependent on amplitude and spectrum of substrate noise. [5] input clock coming from a crys tal oscillator with less than 250 ps peak-to-peak period jitter. 11.7 fro the fro is trimmed to ? 1 % accuracy over the entire voltage and temperature range. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.8 crystal oscillator table 33. dynamic charac teristics of the pll2 [1] symbol parameter conditions min typ max unit reference clock input f in input frequency 1 - 25 mhz clock output f o output frequency for pll2 clkout output [2] 4.3 - 550 mhz d o output duty cycle for pll2 clkout output 46 - 54 % f cco cco frequency 275 - 550 mhz lock detector output ? lock(pfd) pfd lock criterion [3] 124 ns dynamic parameters at f out = f cco = 540 mhz; standard bandwidth settings j rms-interval rms interval jitter f ref = 10 mhz [4][5] -1530 ps j pp-period peak-to-peak, period jitter f ref = 10 mhz [4][5] -4080 ps table 34. dynamic characteristic: fro t amb = ? 40 ? c to +105 ? c; 1.71 v ? v dd ? 3.6 v. symbol parameter conditions min typ [1] max unit f osc(rc) fro clock frequency - 11.88 12 12.12 mhz f osc(rc) fro clock frequency - 47.52 48 48.48 mhz f osc(rc) fro clock frequency - 95.04 96 96.96 mhz table 35. dynamic characteristic: oscillator t amb = ? 40 ? c to +105 ? c; 1.71 v ? v dd ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit low-frequency mode (1-20 mhz) [4] t jit(per) period jitter time 5 mhz crystal [3] - 13.2 - ps 10 mhz crystal - 6.6 - ps 15 mhz crystal - 4.8 - ps
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 116 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [3] indicates rms period jitter. [4] select low frequency range = 0 in the sysoscctrl register. [5] select high frequency = 1 in the sysoscctrl register. 11.9 rtc oscillator see section 13.5 for connecting the rtc oscillator to an external clock source. [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. high-frequency mo de (20 - 25 mhz) [5] t jit(per) period jitter time 20 mhz crystal [3] -4.3- ps 25 mhz crystal - 3.7 - ps table 35. dynamic characteristic: oscillator ?continued t amb = ? 40 ? c to +105 ? c; 1.71 v ? v dd ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit table 36. dynamic characte ristic: rtc oscillator t amb = ? 40 ? c to +105 ? c; 1.71 ? v dd ? 3.6 [1] symbol parameter conditions min typ [1] max unit f i input frequency - - 32.768 - khz
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 117 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.10 watchdog oscillator [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ? 40 ? c to +105 ? c) is ? 40 %. [3] actual jitter dependent on amplitude and spectrum of substrate noise. [4] guaranteed by design. not tested in production samples. table 37. dynamic characteristics: watchdog oscillator t amb = ? 40 ? c to +105 ? c; 1.71 ? v dd ? 3.6 [1] symbol parameter conditions min typ [1] max unit f osc(int) internal watchdog oscillator frequency [2] 200 - 1500 khz d clkout clkout duty cycle 48 - 52 % j pp-cc peak-peak period jitter [3][4] -1 20ns t start start-up time [4] -4 - ? s
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 118 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.11 i 2 c-bus [1] guaranteed by design. not tested in production. [2] parameters are valid over oper ating temperature range unless otherwise specified. see the i 2 c-bus specification um10204 for details. [3] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall times are allowed. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maxi mum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. table 38. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; 1.71 v ? v dd ? 3.6 v. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4][5][6][7] both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3][4][8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9][10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 119 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 27. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 120 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.12 i 2 s-bus interface table 39. dynamic characteristics: i 2 s-bus interface pins [1][4] t amb = ? 40 ? c to 105 ? c; v dd = 1.71 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1.0 ns, slew setting = standard mode for all pins; parameters sampled at the 50 % level of the rising or falling edge. symbol parameter conditions min typ [3] max unit common to master and slave t wh pulse width high on pins i2 sx_tx_sck and i2sx_rx_sck [5] cclk ? 100 mhz (t cyc /2) -1 - (t cyc /2) +1 ns cclk > 100 mhz (t cyc /2) -1 - (t cyc /2) +1 ns t wl pulse width low on pins i2sx_tx_sck and i2sx_rx_sck [5] cclk ? 100 mhz (t cyc /2) -1 - (t cyc /2) +1 ns cclk > 100 mhz (t cyc /2) -1 - (t cyc /2) +1 ns master; 1.71 v ? vdd ? 2.7 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk ? 100 mhz 26.0 - 40.3 ns cclk > 100 mhz 25.0 - 39.0 ns on pin i2sx_ws cclk ? 100 mhz 26.0 - 41.0 ns cclk > 100 mhz 25.0 - 39.6 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk ? 100 mhz 6.1 - - ns cclk > 100 mhz 6.4 - - ns slave; 1.71 v ? vdd ? 2.7 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk ? 100 mhz 18.8 - 37.1 ns cclk > 100 mhz 18.0 - 35.5 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk ? 100 mhz 4.8 - - ns cclk > 100 mhz 4.4 - - ns on pin i2sx_ws cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns on pin i2sx_ws cclk ? 100 mhz 3.2 - - ns cclk > 100 mhz 3.2 - - ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 121 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] based on characterization; not tested in production. [2] clock divider register (div) = 0x0. [3] typical ratings are not guaranteed. [4] the flexcomm interface function clock frequency s hould not be above 48 mhz. see the data rates section in the i 2 s chapter (um11060) to calculate clock and sample rates. [5] based on simulation. not tested in production. master; 2.7 v ? vdd ? 3.6 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk ? 100 mhz 21.4 - 30.4 ns cclk > 100 mhz 20.6 - 28.7 ns on pin i2sx_ws cclk ? 100 mhz 21.1 - 29 ns cclk > 100 mhz 20.3 - 28.3 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk ? 100 mhz 1.3 - - ns cclk > 100 mhz 1.0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk ? 100 mhz 2.9 - - ns cclk > 100 mhz 3.3 - - ns slave; 2.7 v ? vdd ? 3.6 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk ? 100 mhz 13.8 - 23.6 ns cclk > 100 mhz 13 - 21.9 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk ? 100 mhz 4.7 - - ns cclk > 100 mhz 4.2 - - ns on pin i2sx_ws cclk ? 100 mhz 0.9 - - ns cclk > 100 mhz 0.7 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns on pin i2sx_ws cclk ? 100 mhz 1.5 - - ns cclk > 100 mhz 1.3 - - ns table 39. dynamic characteristics: i 2 s-bus interface pins [1][4] t amb = ? 40 ? c to 105 ? c; v dd = 1.71 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1.0 ns, slew setting = standard mode for all pins; parameters sampled at the 50 % level of the rising or falling edge. symbol parameter conditions min typ [3] max unit
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 122 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 28. i 2 s-bus timing (master) fig 29. i 2 s-bus timing (slave) aaa-026799 i2sx_sck i2sx_tx_sda i2sx_ws t cy(clk) t f t r t wh t wl t v(q) t v(q) t su(d) t h(d) i2sx_rx_sda aaa-026800 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t h(d) t wl i2sx_sck i2sx_rx_sda i2sx_ws i2sx_tx_sda t v(q)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 123 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.13 spi interfaces (flexcomm interface 0-9) the actual spi bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for spi master mode is 48 mbit/s, and the maximum supported bit rate for spi slave mode is 14 mbit/s. [1] based on characterization; not tested in production. table 40. spi dynami c characteristics [1] t amb = ? 40 ? c to 105 ? c; 1.71 v ? v dd ? 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew setting = standard mode for all pins;. parameters sampled at the 50 % level of the rising or falling edge. symbol parameter conditions min typ max unit spi master 1.71 v ? v dd ? 2.7 v t ds data set-up time cclk ? 100 mhz 2.2 - - ns cclk > 100 mhz 1.9 - - ns t dh data hold time cclk ? 100 mhz 6.3 - - ns cclk > 100 mhz 6.7 - - ns t v(q) data output valid time cclk ? 100 mhz 2.6 - 5.0 ns cclk > 100 mhz 0.3 - 4.7 ns spi slave 1.71 v ? v dd ? 2.7 v t ds data set-up time cclk ? 100 mhz 1.1 - - ns cclk > 100 mhz 0.9 - - ns t dh data hold time cclk ? 100 mhz 2.1 - - ns cclk > 100 mhz 2.2 - - ns t v(q) data output valid time cclk ? 100 mhz 18.8 - 37.0 ns cclk > 100 mhz 18.0 - 36.0 ns spi master 2.7 v ? v dd ? 3.6 v t ds data set-up time cclk ? 100 mhz 2.4 - - ns cclk > 100 mhz 2.2 - - ns t dh data hold time cclk ? 100 mhz 4.2 - - ns cclk > 100 mhz 4.5 - - ns t v(q) data output valid time cclk ? 100 mhz 1.8 - 4.6 ns cclk > 100 mhz 1.7 - 4.0 ns spi slave 2.7 v ? v dd ? 3.6 v t ds data set-up time cclk ? 100 mhz 1.2 - - ns cclk > 100 mhz 1.0 - - ns t dh data hold time cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t v(q) data output valid time cclk ? 100 mhz 14 - 23.9 ns cclk > 100 mhz 13.3 - 22.2 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 124 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 30. spi master timing sck (cpol = 0) mosi (cpha = 1) ssel miso (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid mosi (cpha = 0) miso (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014969 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 125 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 31. spi slave timing sck (cpol = 0) miso (cpha = 1) ssel mosi (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid miso (cpha = 0) mosi (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014970 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 126 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.14 spi interfaces (flexcomm interface 10) the actual spi bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for spi master mode is 50 mbit/s, and the maximum supported bit rate for spi slave mode is 50 mbit/s. [1] based on characterization; not tested in production. table 41. spi dynamic characteristics [1] t amb = ? 40 ? c to 105 ? c; 1.71 v ? v dd ? 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew setting = standard mode for all pins;. parameters sampled at the 50 % level of the rising or falling edge. symbol parameter conditions min typ max unit spi master t ds data set-up time 0 - - ns t dh data hold time 10.0 - - ns t v(q) data output valid time 0.8 - 10.0 ns spi slave t ds data set-up time 1.2 - - ns t dh data hold time 10.0 - - ns t v(q) data output valid time 4.28 - 10.0 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 127 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 32. spi master timing sck (cpol = 0) mosi (cpha = 1) ssel miso (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid mosi (cpha = 0) miso (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014969 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 128 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 33. spi slave timing sck (cpol = 0) miso (cpha = 1) ssel mosi (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid miso (cpha = 0) mosi (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014970 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 129 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.15 spifi the actual spifi bit rate depends on the dela ys introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the ma ximum supported bit rate for spifi mode is 100 mbit/s. [1] based on simulation; not tested in production. table 42. dynamic characteristics: spifi [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.71 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; parameters sampled at the 50 % level of the rising or falling edge. symbol parameter conditions min typ max unit spifi 1.71 v ? vdd ? 2.7 v t ds data set-up time cclk ? 100 mhz 4 - - ns cclk > 100 mhz 4 - - ns t dh data hold time cclk ? 100 mhz 6.4 - - ns cclk > 100 mhz 6.6 - - ns t v(q) data output valid time cclk ? 100 mhz 5.7 - 13.7 ns cclk > 100 mhz 5.7 - 13.7 ns spifi 2.7 v ? vdd ? 3.6 v t ds data set-up time cclk ? 100 mhz 4 - - ns cclk > 100 mhz 4 - - ns t dh data hold time cclk ? 100 mhz 3.5 - - ns cclk > 100 mhz 3.6 - - ns t v(q) data output valid time cclk ? 100 mhz 3.3 - 11.5 ns cclk > 100 mhz 3.3 - 11.5 ns in mode 0, mode3 bit (23) in spifi ctrl register is set to '0' (default). the spifi drives sck low after the rising edge at which the last bit of eac h command is captured, and keeps it low while cs is high. fig 34. spifi control register (mode 0) spifi_sck spifi data out spifi data in t cy(clk) t ds t dh t v(q) data valid data valid t h(q) data valid data valid 002aah409
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 130 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.16 dmic subsystem [1] based on simulated values. 11.17 smart card interface [1] based on simulated values. v dd = 2.7 v - 3.6 v. table 43. dynamic characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 2.7 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; bypass bit = 0; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ max unit t ds data set-up time cclk ? 100 mhz 14.3 - - ns cclk > 100 mhz 14.3 - - ns t dh data hold time cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns fig 35. dmic timing diagram aaa-017025 clock data t su t dh table 44. dynamic characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.71 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew setting = standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ max unit 2.7 v ? vdd ? 3.6 v t ds data set-up time cclk ? 100 mhz 2.1 - - ns cclk > 100 mhz 2.1 - - ns t dh data hold time cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t v(q) data output valid time cclk ? 100 mhz 11.0 - 22.5 ns cclk > 100 mhz 11.0 - 22.5 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 131 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.18 usart interface the actual usart bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for usart master synchronous mode is 24 mbit/s, and the maximum supported bit rate for usart slave synchronous mode is 12.5 mbit/s. [1] based on characterization; not tested in production. table 45. usart dynamic characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.71 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew setting = standard mode for all pins; parameters sampled at the 50 % level of the rising or falling edge. symbol parameter conditions min typ max unit usart master (in synchronous mode) 1.71 v ? vdd ? 2.7 v t su(d) data input set-up time cclk ? 100 mhz 21.2 - - ns cclk > 100 mhz 19.7 - - ns t h(d) data input hold time cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t v(q) data output valid time cclk ? 100 mhz 0 - 4.9 ns cclk > 100 mhz 0 - 4.5 ns usart slave (in synchronous mode)1.71 v ? vdd ? 2.7 v t su(d) data input set-up time cclk ? 100 mhz 1.7 - - ns cclk > 100 mhz 1.5 - - ns t h(d) data input hold time cclk ? 100 mhz 1.2 - - ns cclk > 100 mhz 1.4 - - ns t v(q) data output valid time cclk ? 100 mhz 20.2 - 39.5 ns cclk > 100 mhz 19.3 - 37.7 ns usart master (in synchronous mode) 2.7 v ? vdd ? 3.6 v t su(d) data input set-up time cclk ? 100 mhz 20.5 - - ns cclk > 100 mhz 18.9 - - ns t h(d) data input hold time cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t v(q) data output valid time cclk ? 100 mhz 1.5 - 3.6 ns cclk > 100 mhz 1.3 - 3.2 ns usart slave (in synchronous mode) 2.7 v ? vdd ? 3.6 v t su(d) data input set-up time cclk ? 100 mhz 1.2 - - ns cclk > 100 mhz 1 - - ns t h(d) data input hold time cclk ? 100 mhz 0 - - ns cclk > 100 mhz 0 - - ns t v(q) data output valid time cclk ? 100 mhz 15.2 - 26.1 ns cclk > 100 mhz 14.3 - 24.2 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 132 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.19 sctimer/pwm output timing 11.20 usb interface characteristics [1] characterized but not implemented as production test. guaranteed by design. fig 36. usart timing un_sclk (clkpol = 0) txd rxd t cy(clk) t su(d) t h(d) t v(q) start bit0 t vq) un_sclk (clkpol = 1) start bit0 bit1 bit1 aaa-015074 table 46. sctimer/pwm output dynamic characteristics t amb = ? 40 ? c to 105 ? c; 1.71 v ? v dd ? 3.6 v c l = 30 pf. simulated skew (over process, voltage, and temperature) of any two sct fixed-pin output signals; sampled at the 90 % and 10 % level of the rising or fallin g edge; values guaranteed by design. symbol parameter conditions min typ max unit t sk(o) output skew time - 3.4 - 4.5 ns table 47. dynamic characteristics: usb0 pins (full-speed) c l = 50 pf; r pu = 1.5 k ? on d+ to v dd , unless otherwise specified; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 4.0 20 ns t f fall time 10 % to 90 % 4.0 20 ns t frfm differential rise and fall time matching t r /t f 90 111.11 % v crs output signal crossover voltage 1.3 2.0 v t feopt source se0 interval of eop see figure 37 160 175 ns t fdeop source jitter for differential transition to se0 transition see figure 37 ? 2+5ns t jr1 receiver jitter to next transition ? 18.5 +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 37 [1] 40 - ns t eopr2 eop width at receiver must accept as eop; see figure 37 [1] 82 --ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 133 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.21 11.22 ethernet avb remark: the timing characteristics of the en et_mdc and enet_mdio signals comply with the ieee standard 802.3 . fig 37. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop table 48. dynamic characteristics: ethernet t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew setting = standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. based on simulation. symbol parameter conditions min typ max unit rmii mode f clk clock frequency for enet_rx_clk [1] - - 50.0 mhz ? clk clock duty cycle [1] 45.0 - 55.0 % t su data input set-up time enet_rxdn, enet_rx_er, enet_rx_dv [1][2] cclk ? 100 mhz 4.4 - - ns cclk > 100 mhz 4.4 - - ns t h data input hold time for enet_rxdn, enet_rx_er, enet_rx_dv [1][2] cclk ? 100 mhz ? 1.3 - 0 ns cclk > 100 mhz ? 1.3 - 0 ns t v(q) data output valid time for enet_txdn, enet_tx_en [1][2] cclk ? 100 mhz 9.9 - 17.3 ns cclk > 100 mhz 9.9 - 17.3 ns mii mode f clk clock frequency for enet_tx_clk [1] - - 25.0 mhz ? clk clock duty cycle [1] 45.0 - 55.0 % f clk clock frequency for enet_rx_clk [1] - - 25.0 mhz ? clk clock duty cycle [1] 45.0 - 55.0 % t su data input set-up time for enet_rxdn, enet_rx_er, enet_rx_dv [1][2] cclk ? 100 mhz 4.7 - - ns cclk > 100 mhz 4.7 - - ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 134 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] output drivers can drive a load ? 25 pf accommodating over 12 inch of pcb trace and the input capacitance of the receiving device. [2] timing values are given from the point at which the cl ock signal waveform crosses 1.4 v to the valid input or output level. t h data input hold time for enet_rxdn, enet_rx_er, enet_rx_dv [1][2] cclk ? 100 mhz ? 1.2 - 0 ns cclk > 100 mhz ? 1.2 - 0 ns t v(q) data output valid time for enet_txdn, enet_tx_en, enet_tx_er [1][2] cclk ? 100 mhz 10.0 - 18.2 ns cclk > 100 mhz 10.0 - 18.2 ns table 48. dynamic characteristics: ethernet t amb = ? 40 ? c to 105 ? c, v dd = 2.7 v to 3.6 v. c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew setting = standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. based on simulation. symbol parameter conditions min typ max unit fig 38. ethernet rmii timing fig 39. ethernet mii timing aaa-025108 t h enet_rx_clk enet_tx_en enet_txdn enet_rxdn enet_rx_dv t su t v(q) aaa-025109 t h enet_rx_clk enet_tx_en enet_tx_clk enet_rx_er enet_txdn enet_rxdn enet_rx_dv t su t v(q)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 135 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.23 sd/mmc and sdio table 49. dynamic characteristics: sd/mmc and sdio t amb = ? 40 ? c to +105 ? c, v dd = 2.7 v to 3.6 v; c l = 20 pf. sample_delay = 0, drv_delay = 0 in the sddelay register, sdioclkctrl = 0x84, sampled at 90 % and 10 % of th e signal level, slew = 1 ns for sd_clk pin, slew = 1 ns for sd_datn and sd_cmd pins. simulated values in high-speed mode. symbol parameter conditions min typ max unit f clk clock frequency on pin sd_clk; data transfer mode - - 50 mhz t su(d) data input set-up time on pins sd_datn as inputs cclk ? 100 mhz 14.4 - - ns cclk > 100 mhz 14.4 - - ns on pins sd_cmd as inputs cclk ? 100 mhz 14.4 - - ns cclk > 100 mhz 14.4 - - ns t h(d) data input hold time on pins sd_datn as inputs cclk ? 100 mhz 1.5 - - ns cclk > 100 mhz 1.5 - - ns on pins sd_cmd as inputs cclk ? 100 mhz 1.5 - - ns cclk > 100 mhz 1.5 - - ns t v(q) data output valid time on pins sd_datn as outputs cclk ? 100 mhz 1.9 - 3.5 ns cclk > 100 mhz 1.9 - 3.5 ns on pins sd_cmd as outputs cclk ? 100 mhz 1.9 - 3.5 ns cclk > 100 mhz 1.9 - 3.5 ns fig 40. sd/mmc and sdio timing 002aag204 sd_clk sd_datn (o) sd_datn (i) t d(qv) t h(d) t su(d) t cy(clk) t h(q) sd_cmd (o) sd_cmd (i)
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 136 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 11.24 lcd table 50. dynamic characteristics: lcd t amb = ? 40 ? c to 105 ? c; v dd = 2.7 v to 3.6 v; c l = 30 pf. simulated values. symbol parameter conditions min typ max unit f clk clock frequency on pin lcd_dclk - - 50 mhz t v(q) data output valid time on all lcd output pins cclk ? 100 mhz 0.9 - 1.6 ns cclk > 100 mhz 0.9 - 1.6 ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 137 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 12. analog characteristics 12.1 bod table 51. bod static characteristics t amb =25 ? c; based on characterization; not tested in production. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion 1.5 - 1.63 v de-assertion 1.55 - 1.69 v reset level 0 assertion 1.5 - 1.62 v de-assertion 1.55 - 1.69 v v th threshold voltage interrupt level 1 assertion 1.54 - 1.68 v de-assertion 1.6 - 1.75 v reset level 1 assertion 1.55 - 1.68 v de-assertion 1.61 - 1.74 v v th threshold voltage interrupt level 2 assertion 1.79 - 1.95 v de-assertion 1.85 - 2.02 v reset level 2 assertion 2.04 - 2.21 v de-assertion 2.19 - 2.38 v v th threshold voltage interrupt level 3 assertion 2.62 - 2.86 v de-assertion 2.77 - 3.03 v reset level 3 assertion 2.62 - 2.85 v de-assertion 2.78 - 3.02 v
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 138 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 12.2 12-bit adc characteristics [1] based on characterization; not tested in production. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [3] the input resistance of adc channels 6 to 11 is higher than adc channels 0 to 5. [4] c ia represents the external capacitance on t he analog input channel for sampling speeds of 5.0 msamples/s. no parasitic capacitances included. [5] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 41 . [6] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 41 . [7] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 41 . table 52. 12-bit adc static characteristics t amb = ? 40 ? c to +105 ? c; 1.71 v ? v dd ? 3.6 v; v ssa = vrefn = gnd. adc calibrated at t amb = 25 ?? c. symbol parameter conditions min typ [2] max unit v ia analog input voltage [3] 0- v dda v c ia analog input capacitance [4] -5.0- pf f clk(adc) adc clock frequency -80 mhz f s sampling frequency - 5.0 5.3 msamples/s e d differential linearity error 2.0 v ? v dda ? 3.6 v 2.0 v < vrefp ? 3.6 v f clk(adc) = 80 mhz [1][5] - ??? 3.0 - lsb 1.71 v ? v dda ? 2.0 v 1.71 v ? vrefp ? 2.0 v f clk(adc) = 80 mhz [1][5] - ??? 4.5 - lsb [1][5] --lsb e l(adj) integral non-linearity 2.0 v ? v dda ? 3.6 v 2.0 v < vrefp ? 3.6 v f clk(adc) = 80 mhz [1][6] - ??? 4.0 - lsb 1.71 v ? v dda ? 2.0 v 1.71 v ? vrefp ? 2.0 v f clk(adc) = 80 mhz [1][6] - ??? 7.5 - lsb [1][6] --lsb e o offset error calibration enabled [1][7] - ??? 2.2 - mv v err(fs) full-scale error voltage 2.0 v ? v dda ? 3.6 v 2.0 v < vrefp ? 3.6 v f clk(adc) = 80 mhz [1][8] - ??? 3.0 - lsb 1.71 v ? v dda ? 2.0 v 1.71 v ? vrefp ? 2.0 v f clk(adc) = 80 mhz - ??? 2.5 - lsb z i input impedance f s = 5.0 msamples/s [9][10] 17.0 - - k ?
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 139 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [8] the full-scale error voltage or gain error (e g ) is the difference between the st raight-line fitting the actual transfer curve after removing offset error, and the stra ight line which fits the ideal transfer curve. see figure 41 . [9] t amb = 25 ? c; maximum sampling frequency f s = 5.0 msamples/s and analog input capacitance c ia =5pf. [10] input impedance z i is inversely proportional to the sampling frequency and the total input capacity including c ia and c io : z i ? 1 / (f s ? c i ). see table 20 for c io . see figure 42 . (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 41. 12-bit adc characteristics aaa-016908 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - vrefn 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 140 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller table 53. adc sampling times [1] -40 ? c ? t amb <= 85 ? c; 1.71 v ? v dda ? 3.6 v; 1.71 v ? v dd ? 3.6 v symbol parameter conditions min typ max unit adc inputs adc_5 to adc_0 (fast channels); adc resolution = 12 bit t s sampling time z o < 0.05 k ? [3] 20 - - ns 0.05 k ? <= z o < 0.1 k ? 23 - - ns 0.1 k ? <= z o < 0.2 k ? 26 - - ns 0.2 k ? <= z o < 0.5 k ? 31 - - ns 0.5 k ? <= z o < 1 k ? 47 - - ns 1 k ? <= z o < 5 k ? 75 - - ns adc inputs adc_5 to adc_0 (fast channels); adc resolution = 10 bit t s sampling time z o < 0.05 k ? [3] 15 - - ns 0.05 k ? <= z o < 0.1 k ? 18 - - ns 0.1 k ? <= z o < 0.2 k ? 20 - - ns 0.2 k ? <= z o < 0.5 k ? 24 - - ns 0.5 k ? <= z o < 1 k ? 38 - - ns 1 k ? <= z o < 5 k ? 62 - - ns adc inputs adc_5 to adc_0 (fast channels); adc resolution = 8 bit t s sampling time z o < 0.05 k ? [3] 12 - - ns 0.05 k ? <= z o < 0.1 k ? 13 - - ns 0.1 k ? <= z o < 0.2 k ? 15 - - ns 0.2 k ? <= z o < 0.5 k ? 19 - - ns 0.5 k ? <= z o < 1 k ? 30 - - ns 1 k ? <= z o < 5 k ? 48 - - ns adc inputs adc_5 to adc_0 (fast channels); adc resolution = 6 bit t s sampling time z o < 0.05 k ? [3] 9- - ns 0.05 k ? <= z o < 0.1 k ? 10 - - ns 0.1 k ? <= z o < 0.2 k ? 11 - - ns 0.2 k ? <= z o < 0.5 k ? 13 - - ns 0.5 k ? <= z o < 1 k ? 22 - - ns 1 k ? <= z o < 5 k ? 36 - - ns adc inputs adc_11 to adc_6 (slow ch annels); adc resolution = 12 bit t s sampling time z o < 0.05 k ? [3] 43 - - ns 0.05 k ? <= z o < 0.1 k ? 46 - - ns 0.1 k ? <= z o < 0.2 k ? 50 - - ns 0.2 k ? <= z o < 0.5 k ? 56 - - ns 0.5 k ? <= z o < 1 k ? 74 - - ns 1 k ? <= z o < 5 k ? 105 - - ns
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 141 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] characterized through simulation. not tested in production. [2] the adc default sampling time is 2.5 adc clock cycles. to match a given analog source output impedance, the sampling time can be extended by addi ng up to seven adc clock cycles for a maximum sampling time of 9.5 adc clock cycles. see the tsamp bits in the adc ctrl register. [3] z o = analog source output impedance. [4] for vdd ? 2.5 v, add one additional cloc k cycle to the values in table 53 . 12.2.1 adc input impedance figure 42 shows the adc input impedance. in this figure: ? adcx represents slow adc input channels 6 to 11. ? adcy represents fast adc input channels 0 to 5. ? r 1 and r sw are the switch-on resistance on the adc input channel. ? if fast channels (adc inputs 0 to 5) are selected, the adc input signal goes through r sw to the sampling capacitor (c ia ). ? if slow channels (adc inputs 6 to 11) are selected, the adc input signal goes through r 1 + r sw to the samplin g capacitor (c ia ). ? typical values, r 1 = 487 ? , r sw = 278 ? ? see ta b l e 2 0 for c io . ? see ta b l e 5 2 for c ia . adc inputs adc_11 to adc_6 (slow ch annels); adc resolution = 10 bit t s sampling time z o < 0.05 k ? [3] 35 - - ns 0.05 k ? <= z o < 0.1 k ? 38 - - ns 0.1 k ? <= z o < 0.2 k ? 40 - - ns 0.2 k ? <= z o < 0.5 k ? 46 - - ns 0.5 k ? <= z o < 1 k ? 61 - - ns 1 k ? <= z o < 5 k ? 86 - - ns adc inputs adc_11 to adc_6 (slow channels); adc resolution = 8 bit t s sampling time z o < 0.05 k ? [3] 27 - - ns 0.05 k ? <= z o < 0.1 k ? 29 - - ns 0.1 k ? <= z o < 0.2 k ? 32 - - ns 0.2 k ? <= z o < 0.5 k ? 36 - - ns 0.5 k ? <= z o < 1 k ? 48 - - ns 1 k ? <= z o < 5 k ? 69 - - ns adc inputs adc_11 to adc_6 (slow channels); adc resolution = 6 bit t s sampling time z o < 0.05 k ? [3] 20 - - ns 0.05 k ? <= z o < 0.1 k ? 22 - - ns 0.1 k ? <= z o < 0.2 k ? 23 - - ns 0.2 k ? <= z o < 0.5 k ? 26 - - ns 0.5 k ? <= z o < 1 k ? 36 - - ns 1 k ? <= z o < 5 k ? 51 - - ns table 53. adc sampling times [1] ?continued -40 ? c ? t amb <= 85 ? c; 1.71 v ? v dda ? 3.6 v; 1.71 v ? v dd ? 3.6 v symbol parameter conditions min typ max unit
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 142 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 12.3 temperature sensor [1] absolute temperature accuracy. [2] based on simulation. fig 42. adc input impedance dac adc r sw r 1 c ia adcx adcy c io c io aaa-017600 table 54. temperature sensor stati c and dynamic characteristics v dd = v dda = 1.71 v to 3.6 v symbol parameter conditions min typ max unit dt sen sensor temperature accuracy t amb = ? 40 ? c to +105 ? c [1] -2.56 ? c e l linearity error t amb = ? 40 ? c to +105 ? c- - 2.56 ? c t s(pu) power-up settling time to 99% of temperature sensor output value [2] - 10.0 15.0 ? s
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 143 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller [1] measured over typical samples. [2] measured for samples over process corners. table 55. temperature sensor linear-least-square (lls) fit parameters v dd = v dda = 1.71 v to 3.6 v fit parameter range min typ max unit lls slope t amb = ? 40 ? c to +105 ? c [1] - ? 2.04 - mv/ ? c lls intercept at 0 ? ct amb = ? 40 ? c to +105 ? c [1] - 584.0 - mv value at 30 ? c [2] 520.3 - 532.7 mv v dd = v dda 3.3 v; measured on matrix samples. fig 43. lls fit of the temperature sensor output voltage ddd 7hpshudwxuh?& 9 r 9 r p9 p 9 p9 //6ilw / / 6 i l w //6ilw
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 144 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13. application information 13.1 start-up behavior figure 44 shows the start-up timing after reset. the fro 12 mhz oscillator provides the default clock at reset and provides a clean system clock shortly af ter the supply pins reach operating voltage. fig 44. start-up timing table 56. typical start-up timing parameters parameter description value t a fro start time ? 20 ? s t b internal reset de-asserted 151 ? s aaa-024049 valid threshold = 1.71 v processor status v dd fro status internal reset gnd boot time user code boot code execution finishes; user code starts fro starts supply ramp-up time t b s t a s t c s
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 145 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.2 standard i/o pi n configuration figure 45 shows the possible pin modes for standard i/o pins: ? digital output driver: enabled/disabled. ? digital input: pull- up enabled/disabled. ? digital input: pull-down enabled/disabled. ? digital input: repeater mode enabled/disabled. ? z mode; high impedance (no cross-bar currents for floating inputs). for initial device revision 0a (boot rom ve rsion 21.0), the default configuration for the standard i/o pins is pu mode (input mode, pull-up enabled, pull-up resistor pulls up pin to vdd). for future device revision 1b (boot rom version 21.1), the default configuration for the standard i/o pins is z mode (high impedance; pull-up or pull-down disabled). see the errata sheet lpc540xx (iocon.1) for more details. the weak mos devices provide a drive capability equivalent to pu ll-up and pull-down resistors. fo r future device revision 1b (boot rom version 21.1), gpio pins pio 0_12, pio0_11, pio 0_2, pio0_3, pio0_4, pio0_5, and pio0_6 have the input buffer enabled (digimode, bit 8 is enabled in iocon register) and will be floati ng by default. if unused, it is recommended to externally terminate this pins to prevent leakage. the glitch filter rejects pulses of typical 12 ns width. fig 45. standard i/o and reset pin configuration data input to core input buffer enable bit ezi pull-up enable bit epun pull-down enable bit epd analog i/o aaa-015595 slew rate bit slew data output from core enable output driver filter select bit zif glitch filter esd esd vdd vss pin
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 146 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.3 connecting power, clo cks, and debug functions figure 46 shows the basic board connections used to power the lpc540xx devices, connect the external crystal and the 32 khz oscillator for the rtc, and provide debug capabilities via the serial wire port.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 147 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller (1) see section 13.6 ? xtal oscillator ? for the values of c1, c2, c3, and c4. (2) position the decoupling capacitors of 0.1 f and 0.01 f as close as possible to the v dd pin. add one set of decoupling capacitors to each v dd pin. (3) position the decoupling capacitors of 0.1 f as close as possible to the vrefn and v dda pins. the 10 f bypass capacitor filters the power line. tie v dda and vrefp to v dd if the adc is not used. tie vrefn to v ss if adc is not used. (4) uses the arm 10-pin interface for swd. (5) when measuring signals of low frequency, use a low-pass filter to remove noise and to improve adc performance. also see ref. 3 . (6) external pull-up resistors on swdio and swclk pins are opt ional because these pins hav e an internal pull-up enabled by default on initial device revision 0a (boot rom version 21.0). for future device revi sion 1b (boot rom version 21.1), these pin s are in high z mode (internal pull-up and pull-down disabled). s ee the errata sheet lpc540xx (iocon.1) for more details. for future device revision 1b (boot rom version 21.1), gpio pins swdio/pio0_12, swclk/pio0_11, pio0_2, pio0_3, pio0_4, pio0_5, and pio0_6 have the input buffer enabled (digimode, bi t 8 is enabled in iocon register) and will be floating by default. if unused, it is recommended to external ly terminate this pins to prevent leakage. (7) position the decoupling capacitor of 0.1 ? f as close as possible to the v bat pin. tie v bat to v dd if not used. fig 46. power, clock, and debug connections swdio/pio0_12 swclk/pio0_11 resetn v ss v ssa pio0_5 adcx rtcxin rtcxout v dd v dda vrefp vrefn lpc 3.3 v 3.3 v (1) (2) (3) (3) (7) (1) dgnd dgnd agnd 1 3 5 7 9 2 4 6 8 10 dgnd dgnd dgnd c3 c4 0.01 f 0.1 f dgnd 10 f 0.1 f agnd agnd agnd 10 f 0.1 f 0.1 f isp select pins n.c. n.c. n.c. swd connector (6) (4) (6) aaa-029082 pio0_4 pio0_6 3.3 v ~10 k - 100 k vbat dgnd 3.3 v 3.3 v 3.3 v 0.1 f xtalin xtalout dgnd c1 c2 (5) ~10 k - 100 k 3.3 v
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 148 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.4 i/o power consumption i/o pins are contributing to the overall dynamic and static power consumption of the part. if pins are configured as digital inputs, a st atic current can flow depending on the voltage level at the pin and the setting of the internal pull-up and pull-down resistors. this current can be calculated using the parameters r pu and r pd given in ta b l e 2 0 for a given input voltage v i . for pins set to output, the current drive strength is given by parameters i oh and i ol in ta b l e 2 0 , but for calculating the total static current, you also need to consider any external loads connected to the pin. i/o pins also contribute to the dynamic power consumption when the pins are switching because the v dd supply provides the current to charge and discharge all internal and external capacitive loads con nected to the pin in addition to powering the i/o circuitry. the contribution from the i/o switching current i sw can be calculated as follows for any given switching frequency f sw if the external capacitive load (c ext ) is known (see ta b l e 2 0 for the internal i/o capacitance): i sw = v dd x f sw x (c io + c ext )
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 149 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.5 rtc oscillator in the rtc oscillator circuit, only the crystal (xtal) and the capacitances c x1 and c x2 need to be connected externally on rtcxin and rtcxout. see figure 47 . for best results, it is very critical to sele ct a matching crystal fo r the on-chip oscillator. load capacitance (cl), series resistance (rs), and drive level (dl) are important parameters to consider while choosing the cr ystal. after selecting the proper crystal, the external load capacitor c x1 and c x2 values can also be gen erally determined by the following expression: c x1 = c x2 = 2c l ? (c pad + c parasitic ) where: c l - crystal load capacitance c pad - pad capacitance of the rtcxin and rtcxout pins (~3 pf). c parasitic ? parasitic or stray capacitance of external circuit. although c parasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. fo r fine tuning, output the rtc clock to the clockout pin and optimize the values of external load capacitors for minimum frequency deviation. fig 47. rtc oscillator components aaa-029083 lpc rtcxin rtcxout c x2 c x1 xtal = c l c p r s l
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 150 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.5.1 rtc printed circuit board (pcb) design guidelines ? connect the crystal and external load capacitors on the pcb as close as possible to the oscillator input and output pins of the chip. ? the length of traces in the o scillation circuit should be as short as possible and must not cross other signal lines. ? ensure that the load capacitors cx1, cx2, and cx3, in case of third overtone crystal usage, have a common ground plane. ? loops must be made as small as possible to minimize the noise coupled in through the pcb and to keep the parasitics as small as possible. ? lay out the ground (gnd) pattern under crystal unit. ? do not lay out other signal lines under crystal unit for multi-layered pcb.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 151 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.6 xtal oscillator in the xtal oscillator circ uit, only the crystal (xtal) and the capacitances c x1 and c x2 need to be connected externally on xtalin and xtalout. see figure 48 . for best results, it is very critical to sele ct a matching crystal fo r the on-chip oscillator. load capacitance (cl), series resistance (rs), and drive level (dl) are important parameters to consider while choosing the cr ystal. after selecting the proper crystal, the external load capacitor c x1 and c x2 values can also be gen erally determined by the following expression: c x1 = c x2 = 2c l ? (c pad + c parasitic ) where: c l - crystal load capacitance c pad - pad capacitance of the xtalin and xtalout pins (~3 pf). c parasitic ? parasitic or stray capacitance of external circuit. although c parasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. for fine tuning, measure the clock on the xtalout pin and optimize the values of external load capacitors for minimum frequency deviation. fig 48. xtal oscillator components aaa-025725 lpcxxxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 152 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 13.6.1 xtal printed circuit board (pcb) design guidelines ? connect the crystal and external load capacitors on the pcb as close as possible to the oscillator input and output pins of the chip. ? the length of traces in the o scillation circuit should be as short as possible and must not cross other signal lines. ? ensure that the load capacitors cx1, cx2, and cx3, in case of third overtone crystal usage, have a common ground plane. ? loops must be made as small as possible to minimize the noise coupled in through the pcb and to keep the parasitics as small as possible. ? lay out the ground (gnd) pattern under crystal unit. ? do not lay out other signal lines under crystal unit for multi-layered pcb. 13.7 suggested usb interface solutions the usb device can be connected to the usb as self-powered device (see figure 49 ) or bus-powered device (see figure 50 ). on the lpc540xx, the usb_vbus pin is 5 v tolerant only when v dd is applied and at operating voltage level. therefore, if the usb_vbus function is connected to the usb connector and the device is self-powered , the usb_vbus pin must be protected for situations when v dd = 0 v. if v dd is always at operating level while vbus = 5 v, the usb_vbus pin can be connected directly to the vbus pin on the usb connector. for systems where v dd can be 0 v and vbus is directly applied to the vbus pin, precautions must be taken to reduce the voltage to below 3.6 v, which is the maximum allowable voltage on the usb_vbus pin in this case. one method is to use a voltage divider to connect the usb_vbus pin to the vbus on the usb connector. the voltage divider ratio s hould be such that the usb_vbus pin is greater than 0.7 v dd to indicate a logic high while below the 3.6 v allowable maximum voltage. for the following operating conditions vbus max = 5.25 v v dd = 3.6 v, the voltage divider should provide a reduction of 3.6 v/5.25 v or ~0.686 v.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 153 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller the internal pull-up (1.5 k ? ) can be enabled by setting the dcon bit in the devcmdstat register to prevent the usb fr om timing out when there is a significant delay between power-up and handling usb traf fic. external circuitry is not required. fig 49. usb interface on a self-powered device where usb_vbus = 5 v lpcxxxx v dd r1 1.5 k aaa-023996 usb-b connector usb_dp usb_dm usb_vbus v ss r s = 33 r s = 33 usb r2 r3 d+ d- two options exist for connecting vbus to the usb_vbus pin: (1) connect the regulator output to usb_vbus. in this case , the usb_vbus signal is high whenever the part is powered. (2) connect the vbus signal directly from t he connector to the usb_vbus pin. in this case, 5 v are applied to the usb_vbus pin while the regulator is ramping up to supply v dd . since the usb_vbus pin is only 5 v tolerant when v dd is at operating level, this connection can degrade the performance of the part over its li fetime. simulation shows that lifetime is reduced to 15 years at t amb = 45 c and 8 years at t amb = 55 c assuming that usb_vbus = 5 v is applied continuously while v dd = 0 v. fig 50. usb interface on a bus-powered device regulator vbus lpcxxxx v dd r1 1.5 k aaa-023997 usb-b connector usb_dp usb_dm v ss usb_vbus (2) usb_vbus (1) usb d- r s = 33 r s = 33 d+
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 154 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 14. package outline fig 51. lqfp208 package unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.15 29.85 1.43 1.08 7 0 o o 0.08 0.12 1 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot459-1 136e30 ms-026 00-02-06 03-02-20 d (1) 28.1 27.9 h d 30.15 29.85 e z 1.43 1.08 d pin 1 index b p e e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale lqfp208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm sot459-1 a max. 1.6
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 155 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 52. lqfp100 package unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 156 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 53. tfbga180 package references outline version european projection issue date iec jedec jeita sot570-3 sot570-3 08-07-09 10-04-15 unit mm max nom min 1.20 1.06 0.95 0.40 0.35 0.30 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.8 10.4 0.15 0.12 a dimensions (mm are the original dimensions) tfbga180: thin fine-pitch ball grid array package; 180 balls 0 5 10 mm scale a 1 a 2 0.80 0.71 0.65 b d e e e 1 10.4 e 2 v w 0.05 y y 1 0.1 ball a1 index area b a d e c y c y 1 x a b c d e f h k g l j m n p 2468101214 135791113 b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m ball a1 index area detail x a a 2 a 1
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 157 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 54. tfbga100 package references outline version european projection issue date iec jedec jeita sot926-1 - - - - - - - - - sot926-1 05-12-09 05-12-22 unit a max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 a 1 dimensions (mm are the original dimensions) tfbga100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm a 2 b d e e 2 7.2 e 0.8 e 1 7.2 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m ball a1 index area a b c d e f h k g j 246810 13579 ball a1 index area b a e d c y c y 1 x detail x a a 1 a 2
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 158 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 15. soldering fig 55. reflow soldering of the lqfp208 package sot459-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp208 package ax bx gx gy hy hx ay by p1 p2 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot459-1_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout 31.300 31.300 28.300 28.300 0.500 0.560 0.280 1.500 0.400 28.500 28.500 31.550 31.550
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 159 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 56. reflow soldering of the lqfp100 package sot407-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp100 package ax bx gx gy hy hx ay by p1 p2 d2 (8 ) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot407-1 solder land c generic footprint pattern refer to the package outline drawing for actual layout 17.300 17.300 14.300 14.300 0.500 0.560 0.280 1.500 0.400 14.500 14.500 17.550 17.550
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 160 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 57. reflow soldering of the tfbga180 package dimensions in mm pslspsrhxhy hx hy sot570-3 solder land plus solder paste occupied area footprint information for reflow soldering of tfbga180 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot570-3_fr 0.80 0.400 0.400 0.550 12.575 12.575
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 161 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller fig 58. reflow soldering of the tfbga100 package dimensions in mm pslspsrhxhy hx hy sot926-1 solder land plus solder paste occupied area footprint information for reflow soldering of tfbga100 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 162 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 16. abbreviations 17. references [1] lpc540xx. user manual um11060. [2] lpc540xx. errata sheet. [3] technical note adc design guidelines: http://www.nxp.com/documents /technical_note/tn00009.pdf table 57. abbreviations acronym description ahb advanced high-performance bus apb advanced peripheral bus api application programming interface dma direct memory access fro oscillator internal free-running oscillator , tuned to the factory specified frequency gpio general purpose input/output fro free running oscillator lsb least significant bit mcu microcontroller unit pdm pulse density modulation pll phase-locked loop spi serial peripheral interface tcp/ip transmission control protocol/inter net protocol ttl transistor-transistor logic usart universal asynchronous receiver/transmitter
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 163 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 18. revision history table 58. revision history document id release date data sheet status change notice supersedes lpc540xx v.1.8 20180622 product data sheet - v.1.7 modifications: ? updated figure 13 ? typical coremark score ((iterati ons/s)/mhz) vs. frequency (mhz) from sramx ? ? updated table 4 ? pin description ?? : description of vrefn and vssa. ? updated table 5 ? termination of unused pins ? : added usb1_id pin. ? updated table 13 ? coremark score ? , typical values. lpc540xx v.1.7 20180426 product data sheet - v.1.6 modifications: ? updated table 4 ?pin descr iption?: vrefn and vssa. lpc540xx v.1.6 20180417 product data sheet - v.1.5 modifications: ? added lpc54016jet100 tfbga100 device. ? updated table 22 ?dynamic characteristic: typical wake-up times from low power modes?: changed t wake at typical for deep-sleep mode to 150 ? s. was 19 ? s. ? updated section 2 ?features and benefits?. a dded text for full-speed usb crystal-less software library: see technical note tn00033 for more details. lpc540xx v.1.5 20180227 product data sheet - v.1.4 modifications: ? updated table 6 ?pin states in different po wer modes?: added table note 3: if vbat> vdd, the external reset pin must be floating to prevent high leakage. ? updated table 15 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: 1.71 v v dd ? 2.2 v. added table note: at hot temperature and below 2.0 v, the supply current increases sl ightly because of reduction of available rbb (reverse body bias) voltage. ? updated table 16 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: 1.71 v v dd ? 2.2 v. ? updated table 17 ?static characteristics: power consumption in deep power-down mode?: added table note 3: if vbat> vdd, the external re set pin must be floating to prevent high leakage. ? updated figure 15 ?deep-sleep mode: typica l supply current idd versus temperature for different supply voltages vdd?: added rema rk: at hot temperature and below 2.0 v, the supply current increases slightly bec ause of reduction of available rbb (reverse body bias) voltage. ? added section 11.14 ?spi interfaces (flexcomm interface 10)?. lpc540xx v.1.4 20180206 product data sheet - v.1.3 modifications: ? updated figure 3 ?lqfp100 package marking?. lpc540xx v.1.3 20180126 product data sheet - v.1.2
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 164 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller modifications: ? updated features in sect ion 7.14.8.2 ?spi serial i/o controller?: ma ximum data rates of 48 mbit/s in master mode for spi functions (flexcomm interface 0-9) and 50 mbit/s in master mode for spi function s (flexcomm interface 10). ? updated section 11.13 ?spi interfaces (f lexcomm interface 0-9)?: the maximum supported bit rate for spi master mode is 48 mbit/s. was 71 mbit/s in master mode. ? updated footnote 2 of table 5 ?t ermination of unused pins?. ? updated table 15 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: changed deep-sleep condi tions for idd supply current, sramx (64 kb) powered for 25 c and 105 c, was 32 kb. ? updated table 16 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: changed deep-sleep condi tions for idd supply current, sramx (64 kb) powered for 25 c and 105 c, was 32 kb. lpc540xx v.1.2 20180104 product data sheet - v.1.1 modifications: ? added figure 13 ?coremark power consumpt ion: typical ma/mhz vs. frequency (mhz) sramx?, figure 14 ?deep-sleep mode: typical supply current idd versus temperature for different supply voltages vdd?, and figure 15 ?deep power-down mode: typical supply current idd versus temperatur e for different supply voltages vdd?. ? updated table 53 ?temperature sensor static and dynamic characteristics? and table 54 ?temperature sensor linear-least-square (lls) fit parameters?. ? updated table 14 ?static characteristics: power consumption in active and sleep mode?: values for i dd supply current coremark code executed from sramx. ? updated table 15 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: values for deep sleep and deep power-down modes. ? updated table 16 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: values for deep sleep and deep power-down modes. ? updated table 17 ?static characteristics: power consumption in deep power-down mode?: value for deep power-down mode. ? updated table notes for table 4 ?pin description?, table 5 ?termination of unused pins?, and table 6 ?pin states in different power modes?. ? updated text in section 13.2 ?standard i/o pin configuration?. ? added text to table note 4 of figure 43 ?power, clock, and debug connections?. lpc540xx v.1.1 20171207 product data sheet - v.1.0 modifications: ? removed figure 12 through figure 15. lpc540xx v.1 20171128 product data sheet - - table 58. revision history ?continued document id release date data sheet status change notice supersedes
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 165 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1][2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 166 of 168 nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc540xx all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 1.8 ? 22 june 2018 167 of 168 continued >> nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 5 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 pinning information . . . . . . . . . . . . . . . . . . . . . 11 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.1 termination of unused pins. . . . . . . . . . . . . . . 54 6.2.2 pin states in different power modes . . . . . . . . 55 7 functional description . . . . . . . . . . . . . . . . . . 56 7.1 architectural overview . . . . . . . . . . . . . . . . . . 56 7.2 arm cortex-m4 processor . . . . . . . . . . . . . . . 56 7.3 arm cortex-m4 integrat ed floating point unit (fpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.4 memory protection unit (mpu). . . . . . . . . . . . 56 7.5 nested vectored interr upt controller (nvic) for cortex-m4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.5.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 57 7.6 system tick timer (systick) . . . . . . . . . . . . . . 57 7.7 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 57 7.8 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.9 memory mapping . . . . . . . . . . . . . . . . . . . . . . 58 7.10 system control . . . . . . . . . . . . . . . . . . . . . . . . 61 7.10.1 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.10.1.1 free running oscillator (fro) . . . . . . . . . . . . 61 7.10.1.2 watchdog oscillator (wdosc) . . . . . . . . . . . . 61 7.10.1.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 62 7.10.2 system pll (pll0) . . . . . . . . . . . . . . . . . . . . 62 7.10.3 usb pll (pll1) . . . . . . . . . . . . . . . . . . . . . . . 62 7.10.4 audio pll (pll2) . . . . . . . . . . . . . . . . . . . . . . 62 7.10.5 clock generation . . . . . . . . . . . . . . . . . . . . . . 63 7.10.6 brownout detection . . . . . . . . . . . . . . . . . . . . . 65 7.10.7 safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.11 power control . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.11.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.11.2 deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 65 7.11.3 deep power-down mode . . . . . . . . . . . . . . . . 65 7.12 general purpose i/o (gpio) . . . . . . . . . . . . . 68 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.13 pin interrupt/pattern engine . . . . . . . . . . . . . . 68 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.14 serial peripherals . . . . . . . . . . . . . . . . . . . . . . 69 7.14.1 full-speed usb host/device interface (usb0) . . 69 7.14.1.1 usb0 device controller . . . . . . . . . . . . . . . . . 69 7.14.1.2 usb0 host controller . . . . . . . . . . . . . . . . . . . 70 7.14.2 high-speed usb host/device interface (usb1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.14.2.1 usb1 device controller . . . . . . . . . . . . . . . . . 70 7.14.2.2 usb1 host controller . . . . . . . . . . . . . . . . . . . 70 7.14.3 ethernet avb . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.14.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.14.4 spi flash interface (spifi) . . . . . . . . . . . . . . 71 7.14.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.14.5 can flexible data (can fd) interface . . . . . 72 7.14.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.14.6 dmic subsystem . . . . . . . . . . . . . . . . . . . . . . 72 7.14.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.14.7 smart card interface. . . . . . . . . . . . . . . . . . . . 72 7.14.7.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.14.8 flexcomm interface serial communication. . . 72 7.14.8.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.14.8.2 spi serial i/o controller . . . . . . . . . . . . . . . . . 73 7.14.8.3 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 73 7.14.8.4 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.14.8.5 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . 74 7.15 digital peripheral . . . . . . . . . . . . . . . . . . . . . . 75 7.15.1 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . 75 7.15.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.15.2 sd/mmc card interface . . . . . . . . . . . . . . . . . 76 7.15.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.15.3 external memory controller . . . . . . . . . . . . . . 76 7.15.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.15.4 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 78 7.15.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.16 counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 78 7.16.1 general-purpose 32-bit timers/external event counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.16.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.16.2 sctimer/pwm . . . . . . . . . . . . . . . . . . . . . . . . 79 7.16.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.16.3 windowed watchdog ti mer (wwdt) . . . . . . 80 7.16.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.16.4 real time clock (rtc) timer . . . . . . . . . . . . . 80 7.16.5 multi-rate timer (mrt) . . . . . . . . . . . . . . . . . 80 7.16.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.16.6 repetitive interrupt timer (rit) . . . . . . . . . . . 81 7.16.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.17 12-bit analog-to-digital converter (adc). . . . 81 7.17.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.18 crc engine . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.18.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
nxp semiconductors lpc540xx 32-bit arm cortex-m4 microcontroller ? nxp semiconductors n.v. 2018. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 22 june 2018 document identifier: lpc540xx please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7.19 temperature sensor . . . . . . . . . . . . . . . . . . . . 82 7.20 security features. . . . . . . . . . . . . . . . . . . . . . . 82 7.20.1 sha-1 and sha-2 . . . . . . . . . . . . . . . . . . . . . 82 7.20.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.21 emulation and debugging . . . . . . . . . . . . . . . . 83 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 84 9 thermal characteristics . . . . . . . . . . . . . . . . . 87 10 static characteristics. . . . . . . . . . . . . . . . . . . . 88 10.1 general operating conditions . . . . . . . . . . . . . 88 10.2 coremark data . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3 power consumption . . . . . . . . . . . . . . . . . . . . 90 10.4 pin characteristics . . . . . . . . . . . . . . . . . . . . . 96 10.4.1 electrical pin characteristics . . . . . . . . . . . . . . 99 11 dynamic characteristics . . . . . . . . . . . . . . . . 102 11.1 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.2 wake-up process . . . . . . . . . . . . . . . . . . . . . 103 11.3 external memory interface . . . . . . . . . . . . . . 104 11.4 system pll (pll0) . . . . . . . . . . . . . . . . . . . 113 11.5 usb pll (pll1) . . . . . . . . . . . . . . . . . . . . . 114 11.6 audio pll (pll2) . . . . . . . . . . . . . . . . . . . . . 114 11.7 fro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.8 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 115 11.9 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 116 11.10 watchdog oscillator . . . . . . . . . . . . . . . . . . . 117 11.11 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.12 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . 120 11.13 spi interfaces (flexcomm interface 0-9) . . . 123 11.14 spi interfaces (flexcomm interface 10) . . . . 126 11.15 spifi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.16 dmic subsystem . . . . . . . . . . . . . . . . . . . . . 130 11.17 smart card interface . . . . . . . . . . . . . . . . . . . 130 11.18 usart interface. . . . . . . . . . . . . . . . . . . . . . 131 11.19 sctimer/pwm output timing . . . . . . . . . . . . 132 11.20 usb interface characteristics . . . . . . . . . . . . 132 11.22 ethernet avb . . . . . . . . . . . . . . . . . . . . . . . . 133 11.23 sd/mmc and sdio . . . . . . . . . . . . . . . . . . . 135 11.24 lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12 analog characteristics . . . . . . . . . . . . . . . . . 137 12.1 bod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.2 12-bit adc characteristics . . . . . . . . . . . . . . 138 12.2.1 adc input impedance. . . . . . . . . . . . . . . . . . 141 12.3 temperature sensor . . . . . . . . . . . . . . . . . . . 142 13 application information. . . . . . . . . . . . . . . . . 144 13.1 start-up behavior . . . . . . . . . . . . . . . . . . . . . 144 13.2 standard i/o pin configurat ion . . . . . . . . . . . 145 13.3 connecting power, clocks, and debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.4 i/o power consumption. . . . . . . . . . . . . . . . . 148 13.5 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 149 13.5.1 rtc printed circuit board (pcb) design guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.6 xtal oscillator . . . . . . . . . . . . . . . . . . . . . . . 151 13.6.1 xtal printed circuit board (pcb) design guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.7 suggested usb interface solutions . . . . . . . 152 14 package outline. . . . . . . . . . . . . . . . . . . . . . . 154 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 162 17 references. . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18 revision history . . . . . . . . . . . . . . . . . . . . . . 163 19 legal information . . . . . . . . . . . . . . . . . . . . . 165 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 165 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 165 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 165 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 166 20 contact information . . . . . . . . . . . . . . . . . . . 166 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

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